Noise suppression is achieved by averaging a sequence of repetitive waveforms with correction of frequency distortions, establishing a real time processing of signals. First, the waveforms are processed seriatim, and saved in partitioned memory. Then, the memory contents are merged to form an output digital signal. Initially, an input repetitive signal is sampled with a sampling period T, and divided into K sections along the sampling period so that a k.sup.th section, where 0k<K, coincides with segment [k.Math.T/K, (k1).Math.T/K]. Time displacement detection determines relative positions of trigger pulses and edges of the sampling clock, and the number k of a sampling period section where the trigger pulse appears, keeping k unchanged thereafter. A resultant stream of N.Math.K samples is transmitted through a lowpass filter, followed by decimation by K, to complete the averaging.

Methods and systems for power amplification of time varying envelope signals are disclosed herein. In one embodiment, a plurality of signals with constant envelope generated from the decomposition of the quantized version of a time varying envelope signal are individually amplified and then summed to form a desired time-varying envelope signal. Amplitude, phase and frequency characteristics of one or more of the constituent signals are controlled to provide the desired phase, frequency, and/or amplitude characteristics of the desired time varying envelope signal. In another embodiment, a time-varying envelope signal is decomposed into in-phase and quadrature components that are quantized and decomposed into a plurality of quasi constant or constant envelope constituent signals. The constituent signals are amplified, and then summed to construct an amplified version of the original time-varying envelope signal. The signal amplifiers may be Class A, B, AB, C, D, Class F or Class S amplifiers to provide high amplification efficiency.

The present invention provides a device for processing digital signals. The device comprises a digital signal source configured to output codewords, a converter circuit configured to generate an output signal based on a first codeword received from the digital signal source, and a feed forward circuit configured to generate an output current based on a second codeword received from the digital signal source. The output current generated by the feed forward circuit is connected to a current supply of the converter circuit. The digital signal source is configured to generate the second codeword based on the first codeword in order to compensate for variations of a supply current of the converter circuit.

Disclosed is a harmonic compensation device capable of effectively reducing the harmonic distortion of an analog output signal. The harmonic compensation device includes a harmonic compensator, a mixer, a digital-to-analog converter, and an analog output circuit. The harmonic compensator is configured to generate a digital compensation signal according to a digital input signal, in which the digital compensation signal includes the harmonic components of the digital input signal. The mixer is configured to generate a digital output signal according to the digital input signal and the digital compensation signal. The digital-to-analog converter is configured to generate an analog input signal according to the digital output signal. The analog output circuit is configured to generate an analog output signal according to the analog input signal.

Circuit techniques are disclosed for improving the SFDR of a DAC. In an embodiment, a DAC includes a resistor ladder network operably coupled to input logic circuitry and an output. The input logic circuitry receives a multi-bit input signal and effectively creates a plurality of processed input signals therefrom. The resistor ladder network is configured to receive the plurality of processed input signals and includes a corresponding plurality of current paths. Each current path includes: a current switch operably controlled by one of the processed input signals; a first resistor in series with the current switch; a second resistor in series with the first resistor; and a feedforward capacitor in parallel with the second resistor. The output is operably coupled to each of the plurality of current paths and is configured to output an analog output signal that corresponds to the multi-bit input signal.

This invention provides a multi-bit digitally controlled accurate current source circuit including a reference current detection unit, a voltage buffer unit, a digital logic control unit, a switch array unit, and a current source array unit. The reference current detection unit generates a first bias voltage according to a reference current; the voltage buffer unit receives the first bias voltage, and generate a buffer voltage accordingly; the digital logic control unit receives the buffer voltage, and generate a digital control signal accordingly; the switch array unit receives the digital control signal, and generate on-off signals accordingly; and the current source array unit receives and responds to the on-off signals so as to control turn-on and turn-off of the current sources in the current source array unit. In this invention, by adding only one voltage buffer, a cascode current source if formed, and an area saving accurate current source is realized.

A converter system comprises a digital-to-analog converter that has at least one digital input and at least one analog output. The converter system comprises a sample rate module configured to generate a sample rate used for digital-to-analog conversion of digital input data received via the at least one digital input. The sample rate module is configured to modulate the sample rate. The converter system is configured to manipulate the digital input data with respect to the modulation of the sample rate. Further, a method of converting digital input data into an analog signal is described.

A DA converter to reduce second-order harmonic distortion more precisely with convenient configurations. A DA converter including: a DA converting unit to input reference voltage and a digital value and output an analog signal according to the digital value based on the reference voltage; and a superimposing unit to superimpose, on the reference voltage, a superimposing signal based on the analog signal that is output from the DA converting unit, and a DA converting method are provided. The DA converter may further include a setting input unit to input setting regarding at least one of a superimposing amount and a sign of an analog signal to be included in the superimposing signal. Also, an adjusting apparatus and an adjusting method to adjust the DA converter are provided.

Disclosed is a harmonic compensation device capable of effectively reducing the harmonic distortion of an analog output signal. The harmonic compensation device includes a harmonic compensator, a mixer, a digital-to-analog converter, and an analog output circuit. The harmonic compensator is configured to generate a digital compensation signal according to a digital input signal, in which the digital compensation signal includes the harmonic components of the digital input signal. The mixer is configured to generate a digital output signal according to the digital input signal and the digital compensation signal. The digital-to-analog converter is configured to generate an analog input signal according to the digital output signal. The analog output circuit is configured to generate an analog output signal according to the analog input signal.

An ACD device comprises a comparator having an output, a first input, and a second input. The ADC includes a successive approximation register (SAR) configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage V.sub.ref=N*VDD, where N<1. The ADC also includes a digital-to-analog converter (DAC) configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a supply (VDD), and one or more first capacitors also coupled to a supply (VDD) and associated with at least the MSB, and a plurality of second capacitors coupled to a reference (Vref), where Vref=N*VDD, where N<1, wherein the first capacitor having a capacitive value that is equal to (1N) times the total capacitance of a parallel combination of the one or more first capacitors, the second capacitors associated with less significant bits, and an input voltage line carrying an input voltage (V.sub.IN) signal as the second input to the comparator.