Described herein are DACs with low distortion for high dynamic range (HDR), extremely high dynamic range (EHDR), and other suitable applications. Some embodiments relate to a device including a DAC configured for coupling to an amplifier via a force path and a sense path. For example, the DAC may provide output current to the amplifier via the force path, and the DAC may sense the input voltage of the amplifier via the sense path. Accordingly, distortion such as harmonic distortion and/or gain offset from parasitic impedances in the force and/or sense paths may be reduced or eliminated. Some embodiments relate to a DAC including a voltage reference generator configured to compensate for variations in impedances of the DAC, such as due to semiconductor process variation. Accordingly, distortion in the DAC output due to variations in the DAC impedances may be reduced or eliminated.

Various embodiments of the present technology may comprise methods and apparatus for an amplifier circuit. Methods and apparatus for an amplifier circuit according to various aspects of the present invention may be utilized in a digital-to-analog converter. The amplifier circuit may comprise a first operational amplifier with a feedback circuit. The feedback circuit may comprise an inverting amplifier circuit.

This invention provides a multi-bit digitally controlled accurate current source circuit including a reference current detection unit, a voltage buffer unit, a digital logic control unit, a switch array unit, and a current source array unit. The reference current detection unit generates a first bias voltage according to a reference current; the voltage buffer unit receives the first bias voltage, and generate a buffer voltage accordingly; the digital logic control unit receives the buffer voltage, and generate a digital control signal accordingly; the switch array unit receives the digital control signal, and generate on-off signals accordingly; and the current source array unit receives and responds to the on-off signals so as to control turn-on and turn-off of the current sources in the current source array unit. In this invention, by adding only one voltage buffer, a cascode current source if formed, and an area saving accurate current source is realized.

An analog conditioning circuit and a corresponding method for processing an analog input signal provide a conditioned analog signal for input into an analog processing circuit. The analog conditioning circuit comprises a main signal path between an input for receiving the analog input signal and an output for outputting the conditioned analog signal, wherein the transfer function of the main signal path is constrained by a transfer function requirement associated with the analog processing circuit; and a feedforward signal path comprising a first filtering block configured to attenuate desired frequencies of a first signal derived from the analog input signal to provide a filtered analog signal; wherein the feedforward signal path is configured to input the filtered analog signal into the main signal path such that the filtered analog signal is subtracted from a second signal derived from the analog input signal to provide the conditioned analog signal.

Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may include at least two processing paths, each including at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may include adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.

A phase-shifted sampling circuit is described. The phase-shifted sampling circuit includes a primary sampler circuit, an ADC circuit, and an equalization circuit. The primary sampler circuit includes an analog signal input, a first signal path, and a second signal path. The equalization circuit includes a primary sampler equalizer sub-circuit. The primary sampler equalizer sub-circuit is configured to compensate a mismatch between a transfer function associated with the first signal path and a transfer function associated with the second signal path. Further, a method of determining filter coefficients of an equalization circuit of a phase-shifted sampling circuit is described.

A hybrid analog-digital electronic circuit for solving non-linear programming problems includes an analog circuit and a digital microcontroller interconnected to each other by an analog-to-digital converter (ADC) and a digital-to-analog converter (DAC). The analog circuit physically realizes a nonlinear programming problem (NLP) where voltages in the analog circuit represent variables in the NLP, and the interconnection of the analog circuit components enforce Karush-Kuhn-Tucke r (KKT) conditions on the variables, such that the voltages in the analog circuit that represent the variables of the NLP naturally converge to an optimal and feasible solution of the NLP. The digital microcontroller sets the voltages in the analog circuit at particular nodes in the analog circuit through the DAC, where the voltages set at the particular nodes determine a precise cost function to be minimized by the analog circuit, where the voltages set at the particular nodes are computed by the digital microcontroller based on measurements obtained from the analog circuit through the ADC.

A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.

An analog-to-digital converter with noise elimination is disclosed. The analog-to-digital converter converts a single-ended analog input into digital representation, and comprises an input buffer and an analog-to-digital conversion module. The input buffer outputs a positive differential signal and a negative differential signal based on the single-ended analog input. The analog-to-digital conversion module receives the positive differential signal and the negative differential signal to generate the digital representation. The input buffer further transmits a noise compensation signal to the analog-to-digital conversion module. The noise compensation signal contains noise information about noise transmitted from the input buffer to the analog-to-digital conversion module through the positive differential signal and the negative differential signal. The analog-to-digital conversion module uses the noise compensation signal to compensate for the noise transmitted from the input buffer to the analog-to-digital conversion module through the positive differential signal and the negative differential signal.

An analog-to-digital converter (ADC) includes a first controlled oscillator (CO) for generating at least one phase signal, and wherein the at least one phase signal generates a first output signal of the ADC; and at least one first frequency-controlled resistor (FDR) for receiving the at least one phase signal generated by the first CO, wherein the first CO and the at least one first FDR are coupled together at a first subtraction node of the ADC, and wherein the first subtraction node receives a first input signal.