An ADC device comprises a comparator having an output, a first input, and a second input. And the ADC includes a SAR configured to receive the output of the comparator as an input and to generate based thereon a parallel digital output having a most significant bit (MSB) and a plurality of less significant bits associated with a reference voltage. The ADC also includes a DAC configured to receive the parallel digital output from the SAR and to generate based thereon an internal analog signal, the internal analog signal applied as the first input to the comparator. The DAC further includes a capacitor network coupled to the first input having a redistribution capacitor coupled to a first voltage that is greater than the reference voltage such that a ratio N is equal to the reference voltage divided by the first voltage. The DAC also includes one or more first capacitors also coupled to the first voltage, where at least one first capacitor is associated with the MSB. The DAC further including and a plurality of second capacitors coupled to the reference voltage, wherein the redistribution capacitor having a capacitive value that is equal to (1N) times the total capacitance of a parallel combination of the one or more first capacitors. And the second capacitors are associated with less significant bits, and an input voltage line carrying an input voltage (V.sub.IN) switchably coupled to the first input or switchably coupled to the second input.

An analog to digital conversion apparatus that includes an analog to digital converter (ADC), a linearity calculating module and a calibration module is provided. The ADC includes a capacitor array, a comparator and a control circuit. The capacitor array receives an input signal to perform a capacitor-switching to generate a capacitor array output signal. The comparator compares the capacitor array output signal and a comparing signal to generate a digital code output result. The control circuit controls the capacitor-switching according to the digital code output result. The linearity calculating module generates a linearity related parameter according to the digital code output result. The calibration module generates a weighting parameter according to the linearity related parameter when the linearity related parameter is not within a predetermined range to adjust the digital code output result based on the weighting parameter to generate an adjusted digital code output result.

An analog-to-digital converter with noise elimination is disclosed. The analog-to-digital converter converts a single-ended analog input into digital representation, and comprises an input buffer and an analog-to-digital conversion module. The input buffer outputs a positive differential signal and a negative differential signal based on the single-ended analog input. The analog-to-digital conversion module receives the positive differential signal and the negative differential signal to generate the digital representation. The input buffer further transmits a noise compensation signal to the analog-to-digital conversion module. The noise compensation signal contains noise information about noise transmitted from the input buffer to the analog-to-digital conversion module through the positive differential signal and the negative differential signal. The analog-to-digital conversion module uses the noise compensation signal to compensate for the noise transmitted from the input buffer to the analog-to-digital conversion module through the positive differential signal and the negative differential signal.

Systems and methods are provided for clocking scheme to reduce nonlinear distortion. An example system may comprise at least two processing paths, each comprising at least one circuit exhibiting nonlinear behavior. Nonlinearity may be managed during processing of signals, such as by assessing effects of the nonlinear behavior during the processing of signals, and controlling clocking applied via at least one path based on the assessed effects, to reduce the effects of the nonlinear behavior during the processing of signals, eliminating the need for post-processing corrections. The controlling of clocking may comprise adjusting timing of a clock applied in the at least path, such as by introducing a timing-delay adjustment to a clock when the clock is applied to a circuit after the circuit exhibiting nonlinear behavior. A timing-advancement may be applied to signals processed via the at least one path, particularly before the circuit exhibiting nonlinear behavior.

Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.

Disclosed herein is a digital to analog converter including a first dynamic latch receiving a data signal and an inverse of the data signal. The first dynamic latch is clocked by a clock signal and configured to generate first and second quad switching control signals as a function of the data signal and the inverse of the data signal. A second dynamic latch receives the data signal and the inverse of the data signal, is clocked by an inverse of the clock signal, and is configured to generate third and fourth quad switching control signals as a function of the data signal and the inverse of the data signal. A quad switching bit cell is configured to generate an analog representation of the data signal as a function of the first, second, third, and fourth quad switching signals.

A method comprises at least the following steps: generating pseudo random noise in the digital domain coded on a number N of bits, sampled at a given frequency FH/N; multiplexing in the digital domain the binary signals produced by each of the N bits at a sampling frequency FH so as to obtain noise coded on one bit at said frequency FH; transferring the noise thus coded into the analog domain via a low-voltage differential transmission interface; filtering the analog signal in a passband which can be centered on half the sampling frequency of an analog-digital converter.

A transmitter includes a first circuit to generate multiphase pulses, and a second circuit to mix a set of in-phase (I) data and quadrature (Q) data with the multiphase pulses and to generate an output radiofrequency (RF) signal. The multiple pulses include multiple I pulses and multiple Q pulses each comprising a pulse that includes a duty cycle such that a first null appears at a third harmonic frequency in a frequency spectrum of the pulse.

A digital signal processor that is capable of suppressing a signal level of an input analog signal at not more than the maximum voltage for A/D conversion and capable of preventing distortion of an A/D converted digital signal while maintaining a good S/N ratio. The digital signal processor 2 of the present invention includes amplification factor setting mechanisms to set amplification factors of the analog amplifiers to second amplification factors lower than first amplification factors specified by amplification factor adjustment knobs, digital amplifier mechanisms to amplify A/D converted digital signals by third amplification factors lower than the first amplification factors, and digital limiter mechanisms to compare the signal levels of the digital signals amplified by the third amplification factors with a threshold defined in advance and attenuate the digital signals within the range of the third amplification factors based on a result of the comparison.

A device for digitizing an analog signal, wherein a distortion signal outlet of a distortion signal generator is only coupled to an analog digital converter by passive components.