A mechanism is included for jointly determining filter coefficients for Finite Impulse Response (FIR) filters in a Linear, Memory-less Non-linear (LNL), Linear compensator. Calibration signals are applied to a signal converter input in a test and measurement system. Non-linear signal components are determined in signal output from the signal converter. Non-linear filter components are determined at the LNL compensator based on the calibration signals. The non-linear signal components are then compared to the non-linear filter components. The comparison is then resolved to determine filter coefficients for first stage Finite Impulse Response (FIR) filters and second stage FIR filters in the LNL.

Pipelined analog-to-digital converters (ADCs) include a flash ADC that reduces noise tones in power supply current drawn by the flash ADC. A pipelined analog-to-digital converter (ADC) includes a flash ADC and error correction circuitry coupled to the flash ADC. The flash ADC includes a plurality of latched comparators and a plurality of driver circuits. Each of the latched comparators includes an inverting output and a non-inverting output. Each of the driver circuits is coupled to one of the latched comparators, and includes an input terminal and an output terminal. In a first subset of the driver circuits the input terminal is coupled to the inverting output of one of the latched comparators. In a second subset of the driver circuits the input terminal is coupled to the non-inverting output of one of the latched comparators.

An analog to digital conversion apparatus that includes an analog to digital converter (ADC), a linearity calculating module and a calibration module is provided. The ADC includes a capacitor array, a comparator and a control circuit. The capacitor array receives an input signal to perform a capacitor-switching to generate a capacitor array output signal. The comparator compares the capacitor array output signal and a comparing signal to generate a digital code output result. The control circuit controls the capacitor-switching according to the digital code output result. The linearity calculating module generates a linearity related parameter according to the digital code output result. The calibration module generates a weighting parameter according to the linearity related parameter when the linearity related parameter is not within a predetermined range to adjust the digital code output result based on the weighting parameter to generate an adjusted digital code output result.

An input buffer for an analog-to-digital converter, ADC, is provided. The input buffer is configured for receiving an input signal (V.sub.in) and for outputting an output signal (V.sub.out), and comprises an nMOS transistor and pMOS transistor. The nMOS transistor and the pMOS transistor are arranged in a push-pull configuration such that the input signal is fed to gates of the nMOS transistor and the pMOS transistor and the output signal is taken from sources of the nMOS and the pMOS transistors. The input buffer comprises a first varactor connected between a gate of the nMOS transistor and a first biasing voltage potential (V.sub.21), and a second varactor connected between a gate of the pMOS transistor and a second biasing voltage potential (V.sub.22), which are configured to reduce a signal amplitude dependency of a capacitance of the input buffer.

Various embodiments of the invention relate to a high accuracy phase shift apparatus. The phase shift apparatus comprises a voltage controlled analog phase shifter, a microcontroller unit (MCU) and a digital-to-analog converter (DAC). The MCU generates a digital control signal, which is converted into an analog control signal by the DAC to control the voltage controlled analog phase shifter to achieve desired phase shift angle. The phase shift apparatus may further incorporate a temperature sensor for temperature compensation. The output from the temperature sensor may be used to modify the reference voltage of the DAC, or alternatively be used to modify the digital control signal from the MCU. By incorporation digitalized control and temperature compensation to an analog phase shifter, the disclosed phase shift apparatus achieves high accuracy digitalized control, a flat phase shift over a wide bandwidth, and a stable phase shift over temperature variation.

According to one aspect, an integrated circuit is provided comprising: a digital-to-analog converter (MDAC) configured to convert a digital word (DIGW) into an analog signal (SDAC), a switching circuit including: a first transistor (PMOS1) having a drain configured to receive the analog signal (SDAC) and a source connected to a drain of a second transistor (PMOS2) and a third transistor (NMOS1) having a drain configured to receive the analog signal (SDAC) and a source connected to a drain of a fourth transistor (NMOS2); a voltage control circuit configured to apply a voltage on the source of the first transistor (PMOS1) and on the source of the third transistor (NMOS1) so as to limit a drain-source voltage of the first transistor (PMOS1) and a drain-source voltage of the third transistor (NMOS1) regardless of the value of said digital word.

A charge transfer digital-to-analog converter includes a differential reference voltage, a pair of capacitors, and switches including a shorting switch. The switches are configured to be switched in successive phases to generate a charge transfer through the capacitors to generate an output corresponding to a digital input. The specific switches activated and deactivated in each phase are selected according to the digital input. Each capacitor of the pair of capacitors is connected to a respective pin for the output. The shorting switch is configured to short the pair of capacitors to create a zero-differential charge on a first side of the capacitors. The shorting switch is implemented with a bootstrap circuit to maintain a constant common mode voltage of the first side of the capacitors while the shorting switch is activated.

A DA converter to reduce second-order harmonic distortion more precisely with convenient configurations. ADA converter including: a DA converting unit to input reference voltage and a digital value and output an analog signal according to the digital value based on the reference voltage; and a superimposing unit to superimpose, on the reference voltage, a superimposing signal based on the analog signal that is output from the DA converting unit, and a DA converting method are provided. The DA converter may further include a setting input unit to input setting regarding at least one of a superimposing amount and a sign of an analog signal to be included in the superimposing signal. Also, an adjusting apparatus and an adjusting method to adjust the DA converter are provided.

Techniques for monitoring a distortion signal of a power amplifier circuit, where the output of a distortion monitoring circuit includes little or no fundamental signal and closely represents the actual distortion of the amplifier circuit of a wired communications system. The power amplifier circuit can generate a distortion feedback signal that does not affect the power amplifier's output power capability, e.g., no inherent loss in the fundamental output of the amplifier. That is, using a distortion monitor circuit, the power amplifier circuit can resolve a distortion feedback signal from the intended output signal of the output power amplifier circuit.

A charge transfer digital-to-analog converter includes a differential reference voltage, a pair of capacitors, and switches including a shorting switch. The switches are configured to be switched in successive phases to generate a charge transfer through the capacitors to generate an output corresponding to a digital input. The specific switches activated and deactivated in each phase are selected according to the digital input. Each capacitor of the pair of capacitors is connected to a respective pin for the output. The shorting switch is configured to short the pair of capacitors to create a zero-differential charge on a first side of the capacitors. The shorting switch is implemented with a bootstrap circuit to maintain a constant common mode voltage of the first side of the capacitors while the shorting switch is activated.