The present application discloses a data converter (112). The data converter includes an input terminus (98), a digital-to-analog (D/A) converter (116) and a mapping unit (114). The input terminus is configured to receive an input signal. The D/A converter includes a plurality of D/A converter units configured to generate an output signal. The mapping unit is coupled between the input terminus and the D/A converter and is configured to cause the plurality of D/A conversion units to be equivalently arranged in a relative order in which the plurality of D/A conversion units are gated according to specific electrical characteristics of the plurality of D/A conversion units for digital-to-analog conversion. The present application further provides an A/D converter, a D/A converter and a related chip.

A Successive Approximation Register Analog-to-Digital Converter (SAR ADC) is disclosed. The SAR ADC includes a switched capacitor array, a buffer, a comparator and a control logic circuit. The switched capacitor array is arranged to sample an input signal according to a switch control signal to generate a sampling signal. The buffer is arranged to generate a common mode voltage. The comparator is arranged to receive the sampling signal and the common mode voltage in order to generate a comparison result. The control logic circuit is arranged to generate an output signal according to the comparison result, and generate the switch control signal to control the switched capacitor array. The control logic circuit further generates an operation control signal to adjust a Miller compensation capacitor inside the buffer. An associated control method is also disclosed.

A voltage-controlled oscillator-based delta-sigma analog-to-digital converter (VCO-based ΔΣ ADC) includes a VCO-based quantizer that includes delay elements to provide VCO outputs based on an analog input signal and combining logic to combine the VCO outputs so as to provide quantized outputs. Detection logic detects saturation of the VCO-based quantizer based on the quantized outputs and at least a portion of the VCO outputs. The VCO-based ΔΣ ADC also includes correction logic to modify the quantized outputs and provide modified quantized outputs in response to the detection logic detecting the saturation of the VCO-based quantizer and to provide the quantized outputs unmodified in the absence of saturation being detected.

An analog converter includes an offset/gain value storage unit that is composed of a nonvolatile memory and stores therein offset/gain values, an operation unit that performs analog-digital conversion by using the offset/gain values in the offset/gain value storage unit as values for an interpolation operation, a previous offset/gain value storage unit that is composed of a nonvolatile memory and stores therein, as previous offset/gain values, the offset/gain values in the offset/gain value storage unit used in the past, wherein the operation unit includes an offset/gain value setting unit that controls setting of the offset/gain values in the offset/gain value storage unit and storage of the previous offset/gain values in the previous offset/gain value storage unit.

In one form, a signal chain circuit includes a signal chain processing circuit between an input for receiving a differential input signal having a first common-mode voltage, and an output for providing a differential output signal having a second, different common-mode voltage. It includes an amplifier with a differential output stage coupled to a differential input stage and having positive and negative output terminals forming its output, and positive and negative feedback terminals. The differential output stage provides a first voltage drop between the positive output terminal and the positive feedback terminal, and a second voltage drop between the negative output terminal and the negative feedback terminal. The common-mode feedback circuit regulates a common-mode voltage between the positive and negative feedback terminals to the second common-mode voltage. In another form, an analog-to-digital converter includes a range extending logic circuit to extend the range of a ring oscillator based analog-to-digital converter.

Methods and apparatus for reducing non-linearity in analog to digital converters are disclosed. An example apparatus includes an analog-to-digital converter to convert an analog signal into a digital signal; and a non-linearity corrector coupled to the analog-to-digital converter to determine a derivative of the digital signal; determine cross terms including a combination of the digital signal and the derivative of the digital signal; and determine a non-linearity term corresponding to a combination of the cross terms.

The systems and methods discussed herein related to digital to analog conversion. A digital to analog conversion circuit can includes a digital input, an analog output, and a cell array. The digital to analog converter can also include an integrator, an analog to digital converter (ADC), and a summer coupled to the ADC, and an adaptation circuit coupled to the summer. The adaption circuit provides controls signals to the cell array.

A digital-to-analog conversion circuit includes an operational amplification module having an operational amplifier connected to an output transistor to form a negative feedback circuit to obtain equal voltages at positive and negative ends. A negative end current flowing into the negative end is proportional to a positive end current flowing into the positive end. An input end of a conversion module is connected in parallel with a first resistor of the operational amplification module to obtain the same voltage as the first resistor, and an analog current proportional to the negative end current and positive end current. An output end of the conversion module is connected with the source of the output transistor and configured to receive the analog current and to make the analog current flow to an output resistor via the drain of the output transistor, to obtain an output current proportional to the positive end current.

A novel and useful digitally intensive event-driven quasi-level crossing (quasi-LC) delta modulator analog to digital converter (ADC) with adaptive resolution (AR) for Internet of Things (IoT) wireless networks. Minimizing the average sampling rate for sparse input signals significantly reduces the power consumed in data transmission, processing, and storage. The AR quasi-LC delta modulator quantizes the residue voltage signal with a 4-bit asynchronous successive approximation register (SAR) sub-ADC, which enables a straightforward implementation of LC and AR algorithms in the digital domain. The modulator achieves data compression by means of a globally signal dependent average sampling rate and achieves AR through a digital multilevel comparison window that overcomes the tradeoff between the dynamic range and the input bandwidth in conventional LC ADCs. Engaging the AR algorithm reduces the average sampling rate by a factor of three at the edge of the modulator's signal bandwidth.

A time gain compensation (TGC) circuit for an ultrasound device includes a first amplifier having an integrating capacitor and a control circuit configured to generate a TGC control signal that controls an integration time of the integrating capacitor, thereby controlling a gain of the first amplifier. The integration time is an amount of time an input signal is coupled to the first amplifier before the input signal is isolated from the first amplifier.