A digital/analog converter (DAC) includes a reference current generator including an internal resistor, and configured to generate reference current according to a resistance value of the internal resistor and a reference voltage, a digital gain block configured to generate a calibrated digital input signal that is obtained by adjusting a digital gain of a digital input signal based on a ratio between a reference resistance value and a resistance value of the internal resistor, and a conversion circuit configured to convert the calibrated digital input signal into an analog output signal, based on the reference current.

A pipeline analog to digital converter (ADC) includes converter circuitries, a detector circuitry, and a clock generator circuit. The converter circuitries sequentially convert an input signal to be digital codes. One of the converter circuitries includes a sub-ADC circuit and a multiplying digital to analog converter (MDAC) circuit. The sub-ADC circuit performs a quantization according to a first signal to generate a corresponding one of the digital codes, in which the first signal is the input signal or a previous stage residue signal. The MDAC circuit processes the corresponding one of the digital codes in response to a first clock signal, in order to generate a current stage residue signal. The detector circuitry detects whether the quantization is complete, in order to generate a control signal. The clock generator circuit adjusts a timing of the first clock signal according to the control signal.

Methods, apparatus, systems and articles of manufacture to increase an integrity of mismatch corrections in an interleaved analog to digital converter are disclosed. An example apparatus includes an instantaneous mismatch estimator that uses an output of an interleaved analog to digital converter to identify a mismatch estimate between two or more component analog to digital converters of the interleaved analog to digital converter. An integrity monitor is to cause the instantaneous mismatch estimator to avoid incorrectly providing the mismatch estimate to a filter, the integrity monitor to instruct the filter to remove the mismatch estimate when the mismatch estimate is detected to be inaccurate.

A sub-ranging SAR ADC has a coarse flash ADC that generates bit values corresponding to MSBs of the digital output value, and a fine SAR ADC that generates bit values corresponding to LSBs of the digital output value. The fine ADC generates successive analog approximation signals for the analog input signal. Meta-stability (MTS) detection circuitry detects a coarse-ADC MTS condition in the coarse ADC if a magnitude of a difference between a current approximation signal and a previous approximation signal is greater than a specified threshold level. A controller controls operations of the sub-ranging ADC to correct for a detected coarse-ADC MTS condition. The MTS detection circuitry includes a positive MTS detector that detects a positive coarse-ADC MTS condition in the coarse ADC and a negative MTS detector that detects a negative coarse-ADC MTS condition in the coarse ADC.

An ADC that may include a sampler that generates a series of current pulses; a group of charge memory units; a de-multiplexor for providing charge packets that reflect the series of current pulses to the group; at least one controller that causes different charge memory units of the group to receive charge packets from different current pulses during reception periods that start and end at points of tome outside the current pulses, a group of PWM modulators that are configured to generate PWM pulses that represent the charge packets stored by the group of charge memory units; and a processor that is configured to generate an output digital signal that represents the input analog signal based on the PWM pulses.

A receiver circuit comprising: an input terminal configured to receive an input-signal; a feedforward-ADC configured to provide a feedforward-digital-signal based on the input-signal; a feedforward-DAC configured to provide a feedforward-analogue-signal based on the feedforward-digital-signal; a feedforward-subtractor configured to provide an error-signal based on the difference between the feedforward-analogue-signal and the input-signal; an error-LNA configured to provide an amplified-error-signal based on the error-signal; an error-ADC configured to provide a digital-amplified-error-signal based on the amplified-error-signal; a mixer configured to down-convert a signal in a signal path between the input terminal and the error-ADC; and an error-cancellation-block configured to provide an error-cancelled-signal based on a difference between the digital-amplified-error-signal and the feedforward-digital-signal.

Methods and devices are provided for circuits. One device includes an adjustment circuit having an adjustable resistor for modifying a resistance value of a resistive device, the adjustment circuit connected to an adjustment terminal of the resistive device. The resistance value of the adjustable resistor changes, when a voltage or charge on the adjustment terminal of the adjustable resistor is changed. The adjustable resistor is a phase change element with an adjusting terminal to which different voltage values are applied for adjusting a conversion device threshold value.

A device includes an amplifier and calibration circuitry coupled to the amplifier. The calibration circuitry is configured to receive calibration values. The calibration circuitry is also configured to generate an output value in response to receiving a timing input.

A time-interleaved analog-to-digital converter (ADC) uses M analog-to-digital converters to sample an analog input signal to produce digital outputs. The M ADCs, operating in a time-interleaved fashion, can increase the sampling speed several times compared to the sampling speed of just one ADC. The time-interleaved ADC can be programmed and reconfigured to trade one performance metric for another. For example, more time can be given to comparator to improve bit error rate or more time can be given to an amplifier for improved settling which improves SNR, SFDR etc. If the time-interleaved converters are randomized, then the amount of ‘color’ in the noise floor shape can also be traded for other performance metrics.

Various embodiments include a time to digital converter device comprising: a medium resolution delay unit including a plurality of buffers, the medium resolution delay unit configured to receive as inputs a reference clock signal and a data clock signal and configured to output a plurality of delayed data clock signals wherein the delay between the plurality of delayed data clock signal is a medium resolution delay value; a fine resolution delay unit including a plurality of cores configured to receive as inputs the reference clock signal and the plurality of delayed data clock signals from the medium resolution delay unit, wherein the plurality of cores includes: a first bank of delays configured to receive one of the plurality of the delayed data clock signals, a second bank of delays configured to receive the reference clock signal, and; and a fast flip flop connected to the outputs of the first bank of delays and the second bank of delays, wherein the output of the fast flip flop is used to check the phase alignment.