An error calibration apparatus and method are provided. The method is adapted for calibrating a machine learning (ML) accelerator. The ML accelerator achieves computation by using an analog circuit. An error between an output value of one or more computing layers of a neural network and a corresponding corrected value is determined. The computation of the computing layers is achieved by the analog circuit. A calibration node is generated according to the error. The calibration node is located at the next layer of the computing layers. The calibration node is used to minimize the error. The calibration node is achieved by a digital circuit. Accordingly, error and distortion of the analog circuit could be reduced.

A system may include ADC circuitry. To test the performance of the ADC circuitry, the system may include ADC testing circuitry coupled to the ADC circuitry. In particular, the ADC testing circuitry may include reference voltage generation circuitry configured to generate reference voltages serving as test voltages for the ADC circuitry. The ADC circuitry may be coupled to a test input for receiving the test voltages via switching circuitry and may be coupled to a main data input for receiving system data via the switching circuitry. Testing may occur during an idling time period of the system and when the switching circuitry couples the test input to the ADC circuitry. Test input voltages corresponding to one or more stages in the ADC circuitry may be provided to the ADC circuitry, and corresponding output values from the ADC circuitry may be compared to an expected value and/or expected threshold values.

Techniques regarding error detection in one or more generated signals based on one or more signal-to-noise ratios are provided. For example, one or more embodiments described herein can include a system, which can include a memory that can store computer executable components. The system can also include a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can include a signal analysis component that can determine a signal-to-noise ratio associated with a generated signal, wherein the signal-to-noise ratio incorporates a signal value based on a reference signal and a noise value based on a difference between the reference signal and an acquired signal.

A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.

Provided are an analog-to-digital (AD) converter, a sensor system, and a test system capable of reducing the time for test processing. AD converter includes input part, AD conversion part, first output part, and second output part. The analog signal output from sensor is input to input part. AD conversion part digitally converts an analog signal to generate first digital data and second digital data. First output part outputs the first digital data to control circuit. Second output part outputs the second digital data to test controller before first output part outputs the first digital data. In the test mode, test controller determines whether or not sensor system including sensor is in an abnormal state on the basis of the second digital data.

Techniques are provided for the generation of a calibration signal for use on an analog to digital converter (ADC). A system implementing the techniques according to an embodiment includes a calibration signal generator configured to generate a calibration tone, located in a first frequency band, in response to a calibration enable signal. The system also includes a signal summing circuit configured to generate an ADC input signal as a sum of a received signal and the calibration tone. The received signal is located in a second frequency band. The system further includes an ADC circuit configured to convert the ADC input signal to a baseband digital output signal and to perform self-calibration, based on the calibration tone, in response to the calibration enable signal. The frequency bands and the amplitude of the calibration tone are chosen to reduce interference between the received signal and the calibration tone.

The present disclosure provides a circuitry. The circuitry includes a comparator and a signal correlated circuit. The comparator includes a first input terminal, a second input terminal, and an output terminal. The signal correlated circuit includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal is coupled to receive a first input signal. The second input terminal is coupled to receive a second input signal independent from the first input signal. The first output terminal is configured to generate a first output signal and to send the first output signal to the first input terminal of the comparator. The second output terminal is configured to generate a second output signal and to send the second output signal to the second input terminal of the comparator. The first output signal and the second output signal are correlated.

An electronic circuit includes first and second channels which respectively receive first and second analog signals. The first channel includes a first digital to analog converter having an output coupled to a first input of a first sign comparator, and the second channel includes a second digital to analog converter. A switch network selectively couples, upon reception of a self-test mode signal signaling a test phase, an output of the second digital to analog converter to a second input of the first sign comparator. A ramp generation circuit supplies to the first digital to analog converter and the second digital to analog converter two identical ramps of digital codes, which are shifted by a programmable offset with respect to one another. A checking circuit issues a test status signal based on the output of the first sign comparator.

A system and method are described herein for configuring an audio distribution system, comprising a Redis server, the Redis server adapted to store Redis data to be used in configuring the audio distribution system; a plurality of audio devices, the plurality of audio devices and Redis server interconnected to form the audio distribution system, wherein each of the plurality of audio devices comprises—at least one processor; an electronic communications interface operatively connected to the at least one processor and adapted to receive data from a user and transfer the data to the at least one processor; and a memory operatively connected with the at least one processor, wherein the memory stores computer-executable instructions that, when executed by the at least one processor, causes the at least one processor in a first audio device to execute a method for configuring the audio distribution system that comprises: establishing communications using the electronic communications interface between the user and the at least one processor of the first audio device, such that data input by the user is received by the at least one processor of the first audio device; establishing communications to each of the remaining plurality of audio devices and Redis server in the audio distribution system; obtaining information from each of the remaining plurality of audio devices with which communications have been established, such information including one or more of an audio device name, part number, serial number, internet protocol address number, and physical location; receiving configuration information from the user that pertains to a specific audio device of the plurality of audio devices in the audio distribution system that, when installed on a specific audio device, causes the specific audio device to operate in a known manner; and copying that configuration information to others of the same specific type of audio device in the audio distribution system.

A sensor interface circuit includes at least two sensor inputs and at least two front-end circuits to obtain sensor signal acquisitions from the at least two sensor inputs; a test circuit configured to test correct functionality of at least part of one of the front end circuits by applying a test input to the front end circuit under test, by reading a test output of the front end circuit, and by comparing the test output with an expected result thus obtaining at least one test result. The test input is applied intermittently between sensor signal acquisitions; a processing device is configured to compare the sensor signal acquisitions from the different sensor inputs and combine the comparison with the at least one test result to evaluate correct functionality of the sensor interface circuit.