An analog-to-digital converter (ADC) includes a coarse ADC that receives an analog input voltage, generates a first digital signal based on the analog input voltage using a successive approximation register (SAR) method, and outputs a residual voltage remaining after the first digital signal is generated. The ADC further includes an amplifier that receives the residual voltage and a test voltage, generates a residual current by amplifying the residual voltage by a predetermined gain, and generates a test current by amplifying the test voltage by the gain. The ADC further includes a fine ADC that receives the residual current and generates a second digital signal based on the residual current using the SAR method, and an auxiliary path that receives the test current and generates a gain correction signal based on the test current. The gain of the amplifier is adjusted based on the gain correction signal.

This invention provides a device fingerprint extraction method based on smart phone sensor, which comprises the following steps: Step I: Data acquisition; Step II: Data preprocessing; Step III: ADC value recovery; Step IV: Gain matrix estimation; Step V: Validity check; Step VI: Device fingerprint ID generation. This invention can accurately extract the device fingerprint and can uniquely identify device when the device fingerprint ID doesn't change when certain devices are sampled for ex-factory setting recovery, machine upgrade and time point testing.

A semiconductor device includes a digital-analog converter provided with a plurality of current cells, and a test circuit electrically connected to the digital-analog converter to test the digital-analog converter. The test circuit includes: a charge information holding circuit that holds, as differential charge information, a difference value between a first charge according to a first current and a second charge according to a second current by at least one or more current cells among the plurality of current cells; a reference voltage generation circuit that generates a reference voltage to be comparative object; and a comparison circuit that compares a determination voltage according to the differential charge information and the reference voltage to output a comparison result.

In some examples, a method includes controlling a first set of switches to deliver a first voltage signal through a first set of capacitors to a common node. The method also includes controlling a second set of switches to deliver a second voltage signal through a second set of capacitors to the common node, wherein the first set of capacitors is electrically connected to the second set of capacitors by the common node. The method further includes measuring a time duration to discharge the common node. The second voltage signal includes an opposing polarity to the first voltage signal.

A configuration circuit for obtaining a digital code includes a controller circuit that generates a plurality of multibit control words. A digitally controlled current source circuit receives a multibit control word generated by the controller circuit. The digitally controlled current source circuit generates an output current that corresponds to the multibit control word in accordance with a predetermined output curve. A test voltage node receives the output current, and a test voltage develops in response to the output current. A reference voltage node develops a reference voltage, the level of which is independent of the multibit control word. A voltage comparison circuit (i) receives the test voltage and the reference voltage, (ii) compares the two voltages to produce a comparison result and (iii) sends the comparison result to the controller circuit. The digital code is obtained by the configuration circuit using the comparison result and the multibit control word.

In an example embodiment, an apparatus includes: a first sampling capacitor and a comparator to compare a sum voltage at a first input terminal to a voltage level at a second input terminal according to a thermometer cycle. The sum voltage is based at least in part on an analog input voltage and a divided reference voltage, where the analog input voltage and the reference voltage (V.sub.REF) are of a first voltage range and the divided reference voltage is according to $\left(\left(2^M-1\right)V_{\mathrm{REF}}/2^M\right),$
to enable the comparator to operate at a second voltage range, the second voltage range less than $V_{\mathrm{REF}}/2^M,$
and M is a number of bits of a digital output to be decided in the thermometer cycle and is greater than one.

Provided is a method for testing a semiconductor device having an A/D converter, the method includes supplying a sinusoidal analog test signal S1 to an A/D converter, storing a group S2 of output codes generated by the A/D converter over a period with an integer K multiple duration of the cycle of the sine wave, in response to the analog test signal S1, and generating a histogram of the stored group S2 of the output codes, and evaluating the A/D converter on the basis of the histogram.

In an embodiment, a circuit includes first and second analog-to-digital conversion circuit path. The first analog-to-digital conversion circuit path is configured to provide first converted digital data from an analog input signal. The second analog-to-digital conversion circuit path is configured to provide second converted digital data from the analog input signal. A comparison circuit is configured to compare the first converted digital data with the second converter digital data and generate a fault based on the comparison to reveal a mismatch between the first and second converted digital data.

A sub-ranging SAR ADC has a coarse flash ADC that generates bit values corresponding to MSBs of the digital output value, and a fine SAR ADC that generates bit values corresponding to LSBs of the digital output value. The fine ADC generates successive analog approximation signals for the analog input signal. Meta-stability (MTS) detection circuitry detects a coarse-ADC MTS condition in the coarse ADC if a magnitude of a difference between a current approximation signal and a previous approximation signal is greater than a specified threshold level. A controller controls operations of the sub-ranging ADC to correct for a detected coarse-ADC MTS condition. The MTS detection circuitry includes a positive MTS detector that detects a positive coarse-ADC MTS condition in the coarse ADC and a negative MTS detector that detects a negative coarse-ADC MTS condition in the coarse ADC.

Methods and devices are provided for circuits. One device includes an adjustment circuit having an adjustable resistor for modifying a resistance value of a resistive device, the adjustment circuit connected to an adjustment terminal of the resistive device. The resistance value of the adjustable resistor changes, when a voltage or charge on the adjustment terminal of the adjustable resistor is changed. The adjustable resistor is a phase change element with an adjusting terminal to which different voltage values are applied for adjusting a conversion device threshold value.