An example analog signal multiplexer includes two differential input signal ports for receiving a first and a second differential input signals, IN1 and IN2. The multiplexer further includes a differential output signal port with two output terminals OUT+ and OUT−, for outputting a signal based on one or more of the input signals IN1 and IN2. Furthermore, the multiplexer includes a pair of load elements, and an additional differential output signal port that has two output terminals TERM+ and TERM−. The load elements are not coupled directly to the output terminals OUT+ and OUT−, but, rather, are coupled to the output terminals of the additional output signal port, TERM+ and TERM−, enabling a modular approach where multiple instances of the multiplexer may be combined on an “as-needed” basis to realize multiplexing between a larger number of differential inputs that a single multiplexer would allow.

A multipath sampling circuit includes an input line electrically having an input voltage, a plurality of voltage amplifiers in parallel electrically with one another, each voltage amplifier having a respective input electrically coupled in series with the input line, each voltage amplifier having a different gain and a different saturation voltage; and a plurality of track-and-hold circuits. The track-and-hold circuits have a first state in which a respective input of each track-and-hold circuit is electrically coupled to an output of a respective amplifier. The track-and-hold circuits have a second state in which the respective input of each track-and-hold circuit is electrically decoupled from the output of the respective amplifier. The track-and-hold circuits can be electrically coupled to a summing circuit, a buffer amplifier, or an operational amplifier.

This analog-to-digital converting device comprises: an input terminal for receiving the analog input signal; an output terminal for issuing the digital output signal; a first successive approximation register analog-to-digital conversion module, called first SAR ADC module, connected to the input terminal; a first feedback module associated to the first SAR ADC module; a second successive approximation register analog-to-digital conversion module, called second SAR ADC module, connected in a cascaded manner to the first SAR ADC module; a second feedback module associated to the second SAR ADC module; and a multiplexing module connected to the first and second SAR ADC modules, to deliver the digital output signal.

The disclosure belongs to the field of integrated circuits, and is used for reducing an area overhead and a power consumption of a pipelined analog-to-digital converter. Each stage of the pipelined analog-to-digital converter according to the disclosure comprises an analogue-to-digital converter, a digital-to-analog converter, a subtractor and an amplifier. According to the disclosure, an amplification time of the pipelined ADC is used for extra quantization, and a number of bits of each ADC is reduced on the premise of not increasing a number of stages of the pipelined ADC, so that a scale of each circuit is greatly reduced, and the power consumption and the area overhead are reduced.

Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of contexts configured for coupling to an ADC, wherein each context having at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of contexts and configured to perform a programmed conversion sequence based on one or more configurable parameters of one or more contexts of the number of contexts. Methods of performing an analog-to-digital (A/D) conversion sequence, and methods of configuring a number of contexts for an analog-to-digital converter (ADC) controller, are also disclosed.

A method for measuring a complex impedance of a plurality of battery cells in a battery pack comprises controlling an excitation current through the plurality of battery cells in the battery pack; receiving, in a single common measurement circuit, a plurality of voltage signals corresponding to the plurality of battery cells; measuring the excitation current; and calculating a complex impedance of each of the battery cells in the plurality of battery cells based on the plurality of voltage signals and the measured excitation current in a single measurement cycle using either one analog-to-digital converter (ADC) per battery cell or two matched ADCs per battery cell.

This analog-to-digital converting device comprises: an input terminal for receiving the analog input signal; an output terminal for issuing the digital output signal; a first successive approximation register analog-to-digital conversion module, called first SAR ADC module, connected to the input terminal; a first feedback module associated to the first SAR ADC module; a second successive approximation register analog-to-digital conversion module, called second SAR ADC module, connected in a cascaded manner to the first SAR ADC module; a second feedback module associated to the second SAR ADC module; and a multiplexing module connected to the first and second SAR ADC modules, to deliver the digital output signal.

An circuit includes: a plurality of analog-to-digital converters (ADCs) and a control chip. The control chip is utilized for instructing a target ADC to output audio data of a target channel during a target period, and utilized for instructing remaining ADCs not to output audio data in the target period. Then, the control chip defines data timing of the target channel and other channels based on the data receiving time point of the audio data of the target channel. The plurality of ADCs would process analog audio signals of a plurality of channels and output audio data of the plurality of channels according to an assigned order configured by the control chip to form a serial data signal. The control chip separates the audio data of different channels from the serial data signal according to the data timing of the plurality of channels.

Systems and methods directed to a quantum processing apparatus are provided. The apparatus comprises M solid-state qubits, where M>1, and control electronics, which are connected to the solid-state qubits. The control electronics comprise one or more qubit readout circuits, where each of the qubit readout circuits is connected to at least one of the solid-state qubits and comprises a downsampling analog-to-digital converter (hereafter DSADC). Each DSADC is configured to downsample analog signals obtained from the at least one of the solid-state qubits. Such a DSADC operates in the n.sup.th Nyquist zone of the spectrum of the analog signals obtained, so as to down-convert such analog signals from the n.sup.th Nyquist zone to the m.sup.th Nyquist zone of the spectrum, where n>m≥1, prior to sampling the analog signals to convert them into digital signals, in operation. One or more embodiments of the invention are further directed to a related method of operating such a quantum processing apparatus.

In at least some examples, an integrated circuit includes an input pin and an analog-to-digital converter (ADC) comprising an input terminal coupled to the input pin and an output terminal. The integrated circuit further includes a logic circuit comprising an input terminal coupled to the output terminal of the ADC, a first output terminal, and a second output terminal. The integrated circuit further includes a resistance circuit. In an example, the resistance circuit includes a resistor coupled between the input pin and a first node, a first switch coupled between the first node and a reference voltage pin, and a second switch coupled between the first node and a ground pin.