Systems and methods relating to analog-to-digital converters. A delay block receives an input signal at the same time as a coarse ADC (CADC) block. The CADC block produces a multi-bit output and this output is applied to a signal processing block. The delay block delays the input signal from being applied to the signal processing block until the output of the CADC block has been applied/configures the signal processing block. The signal processing block may be a signal shifter, the output of which is ultimately applied to a fine ADC (FADC) block. In an alternative, the signal processing block may be the FADC block. Regardless of the configuration, the output of the CADC is delayed until the output of the FADC block is available. The outputs of the CADC and the FADC blocks are then simultaneously applied to an encoder that produces the overall system output.

A circuit includes an analog-to-digital converter (ADC) and a hysteresis circuit. The ADC is configured to generate a series of digital codes. The hysteresis circuit is configured to: (a) determine that a first digital code of the series of digital codes represents a change in a same direction as previous digital codes and store the first digital code in the register; and (b) determine that a second digital code of the series of digital codes represents a change in direction from previous digital codes, determine that the second digital code is less than a hysteresis value different than a preceding digital code, and not store the second digital code in the register.

A Light Detection and Ranging (LIDAR) receiver includes a photodetector array configured to generate a plurality of electrical signals; a receiver circuit including a plurality of readout channels, configured to read out the plurality of electrical signals from the photodetector array, and a plurality of multibit ADCs, wherein each of the plurality of readout channels includes a different one of the plurality of multibit ADCs, and each of the plurality of multibit ADCs is configured to convert at least one of the plurality of electrical signals into an ADC data sample such that the plurality of multibit ADCs generate a sequence of ADC data samples; an encoder coupled to the plurality of readout channels and configured to receive the sequence of ADC data samples and generate a compressed data packet based on the sequence of ADC data samples; and a communication interface configured to transmit the compressed data packet.

A method and system to perform the verification of measures done by a sensor in quasi real-time. The sensor verification may be implemented at two different levelsa functionality level and a measurement level. At the functionality level, a consistency check of information from different variables may be processed at sensor level depending on the functionality of the physical system being measured. At the measurement level, diagnostics may be performed of the circuits present in the measurement path by specific circuitry and at suitable instants of time to guarantee a Fault Tolerant Time Interval while minimizing sample loss. This may be achieved, at least in part, by increasing the measuring sample rate.

The present invention provides an analog-digital hybrid architecture, which performs 256 multiplications and additions at a time. The system comprises 256 Processing Elements (PE) (108), which are arranged in a matrix form (16 rows and 16 columns). The digital inputs (110) are converted to analog signal (114) using digital to analog converters (DAC) (102). One PE (108) produces one analog output (115) which is nothing but the multiplication of the analog input (114) and the digital weight input (112). The implementation of PE is done by using i) capacitors and switches and ii) resistor and switches. The outputs from multiple PEs (108) in a column are connected together to produce one analog MAC output (116). In the similar manner, the system produces 16 MAC outputs (118) corresponding to 16 columns. Analog to digital converters (ADC) (104) are used to convert the analog MAC output (116) to digital form (118).

A binary/digital input module implemented on an integrated circuit (IC) chip has a plurality of input channels and includes, for each input channel, a comparator coupled to receive a scaled input voltage and a scaled threshold voltage and further coupled to provide an output value and a digital isolation circuit for data coupled between the comparator and a respective output pin to provide the output value across an isolation barrier.

Sampler circuitry, having: an input node which receives an input voltage signal; a primary current path connected between high and low voltage supply nodes; a secondary current path connected between high and low voltage supply nodes; current mirror circuitry; and load circuitry having sampler switches which sample a current signal, where the input node is defined along the primary current path, the primary current path configured to carry a primary current dependent on the input voltage signal; the current mirror circuitry includes a primary side and a secondary side, the primary side connected along the primary current path and the secondary side connected along the secondary current path so that a secondary current dependent on the primary current is caused to flow along the secondary current path; and the load circuitry is connected along the secondary current path so that the secondary current at least partly forms the current signal.

An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

An circuit includes: a plurality of analog-to-digital converters (ADCs) and a control chip. The control chip is utilized for instructing a target ADC to output audio data of a target channel during a target period, and utilized for instructing remaining ADCs not to output audio data in the target period. Then, the control chip defines data timing of the target channel and other channels based on the data receiving time point of the audio data of the target channel. The plurality of ADCs would process analog audio signals of a plurality of channels and output audio data of the plurality of channels according to an assigned order configured by the control chip to form a serial data signal. The control chip separates the audio data of different channels from the serial data signal according to the data timing of the plurality of channels.

Aspects of the subject disclosure may include, for example, a process that encodes a number of digital signals representing image data captured by a video camera, the image data being provided by the video camera in accordance with a 4K ultra-high definition (4K-UHD) standard. The number of digital signals are provided to a multiplexing unit that outputs a multiplexed signal including a number of optical wavelengths, the multiplexed signal being transmitted on a single fiber-optic cable unidirectionally from the multiplexing unit to a presentation device. The multiplexed signal is transmitted on the single cable unidirectionally from the proximal end to the distal end. Other embodiments are disclosed.