System for reducing pattern-dependent inter-symbol interference (ISI) are described. These systems may be implemented using complementary metal-oxide-semiconductor (CMOS) transistors. These systems are designed to clamp the voltage propagating along the datapath to a value that is a fraction of the supply voltage. Furthermore, these systems are designed to reduce the time constant of the datapath. One such system comprises a source including a digital-to-analog converter (DAC) and a destination comprising an analog-to-digital converter (ADC). A circuit disposed along the data path from the DAC to the ADC is configured to receive a supply voltage, receive an input signal from the DAC, and produce an output signal based on the input signal by clamping the output signal to a voltage that is a fraction of the supply voltage.

An apparatus includes a functional circuit, including a power supply node, and a test circuit. The functional circuit is configured to operate in a test mode that includes generating respective test output patterns in response to application of a plurality of test stimulus patterns. The test circuit is configured to identify a particular test stimulus pattern of the plurality of test stimulus patterns, and to reapply the particular test stimulus pattern to the functional circuit multiple times. The test circuit is further configured to vary, for each reapplication, a start time of the particular test stimulus pattern in relation to when a voltage level of the power supply node is sampled for that reapplication.

A method and system to perform the verification of measures done by a sensor in quasi real-time. The sensor verification may be implemented at two different levelsa functionality level and a measurement level. At the functionality level, a consistency check of information from different variables may be processed at sensor level depending on the functionality of the physical system being measured. At the measurement level, diagnostics may be performed of the circuits present in the measurement path by specific circuitry and at suitable instants of time to guarantee a Fault Tolerant Time Interval while minimizing sample loss. This may be achieved, at least in part, by increasing the measuring sample rate.

A method and device for controlling a wavelength of a light emitting assembly. The device comprises a microcontroller, a light emitting assembly temperature control unit, an analog-to-digital converter, a digital-to-analog converter, a storage unit, a thermistor of a negative temperature coefficient in a TOSA component, and a TEC assembly. The microcontroller comprises an ADC input interface, a DAC output interface, a GPIO output interface, an external communication interface, and a memory interface. The light emitting assembly temperature control unit comprises a turn-off enable control circuit, a temperature detecting circuit, an error amplification-comparison-compensation unit, a TEC voltage/current limitation circuit, a TEC voltage/current detecting circuit, and a TEC differential voltage driver. The method and device are simple and flexible, implements a precise control of the wavelength, and also considers an adjustment function of the wavelength.

A rotary movement position sensor is presented that includes a first sensor output, a second sensor output, a first signal processing unit, a second signal processing unit, a first system output providing the output of the first signal processing unit or of the second signal processing unit, and a second system output providing the output of the second signal processing unit or of the first signal processing unit. A swapping unit that swaps the first signal processing unit between the first sensor output and first system output to the second sensor output and second system output and simultaneously swaps the second signal processing unit from the second sensor output and second system output to the first sensor output and first system output and vice versa. A method for detecting errors in a position sensor system is also presented.

Aspect of the present disclosure provide for a circuit. In an example, the circuit comprises a multiplexer having a first input, a second input, a control input, and an output. The circuit further comprises a first register having an input coupled to the output of the multiplexer and an output. The circuit further comprises a second register having an input coupled to the output of the first register and an output. The circuit further comprises a subtractor having a first input coupled to the output of the multiplexer and a second input coupled to the output of the second register. The circuit further comprises a third register having an input coupled to the output of the subtractor and an output coupled to the first input of the multiplexer.

System for reducing pattern-dependent inter-symbol interference (ISI) are described. These systems may be implemented using complementary metal-oxide-semiconductor (CMOS) transistors. These systems are designed to clamp the voltage propagating along the datapath to a value that is a fraction of the supply voltage. Furthermore, these systems are designed to reduce the time constant of the datapath. One such system comprises a source including a digital-to-analog converter (DAC) and a destination comprising an analog-to-digital converter (ADC). A circuit disposed along the data path from the DAC to the ADC is configured to receive a supply voltage, receive an input signal from the DAC, and produce an output signal based on the input signal by clamping the output signal to a voltage that is a fraction of the supply voltage.

A switching circuit for checking an analog input circuit of an A/D converter is shown. The switching circuit comprises the analog circuit and a comparator circuit. The analog input circuit is configured to generate a first derived signal S1 and a second derived signal S2 from an analog input signal SE of the analog input circuit. The first derived signal S1 and the second derived signal S2 are input signals for the comparator circuit, but only the first derived signal S1 is an input signal for the A/D converter. The comparator circuit is configured to check whether a deviation of the derived signals S1, S2 from each other lies within a tolerance range TOL and to output an output signal SA depending on the check, which may be further evaluated.

A circuit includes an analog-to-digital converter (ADC) and a hysteresis circuit. The ADC is configured to generate a series of digital codes. The hysteresis circuit is configured to: (a) determine that a first digital code of the series of digital codes represents a change in a same direction as previous digital codes and store the first digital code in the register; and (b) determine that a second digital code of the series of digital codes represents a change in direction from previous digital codes, determine that the second digital code is less than a hysteresis value different than a preceding digital code, and not store the second digital code in the register.

Multipliers are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers. Generally, digital multipliers can operate at high speed with high precision, and synchronously. As the precision and speed of digital multipliers increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes solutions unsuitable for some ML and AI segments, including in portable, mobile, or near edge and near sensor applications. The present invention discloses embodiments of multipliers that arrange data-converters to perform the multiplication function, operating in mixed-mode (both digital and analog), and capable of low power consumptions and asynchronous operations, which makes them suitable for low power ML and AI applications.