An analog-to-digital conversion devices and methods that approach a linear relationship between resolution and oversampling rate. The process involves modulating an input analog signals with an essentially chaotic encoding signal that is deterministic, aperiodic in that it lacks spectral tones above a threshold, and bounded. The resulting encoded signal is quantized into a bit stream and decoded by applying to that bit stream a non-linear estimation related to said chaotic signal to thereby produce an output representing said input analog signal in digital form.

An optical network includes a transmitting portion configured to (i) encode an input digitized sequence of data samples into a quantized sequence of data samples having a first number of digits per sample, (ii) map the quantized sequence of data samples into a compressed sequence of data samples having a second number of digits per sample, the second number being lower than the first number, and (iii) modulate the compressed sequence of data samples and transmit the modulated sequence over a digital optical link. The optical network further includes a receiving portion configured to (i) receive and demodulate the modulated sequence from the digital optical link, (ii) map the demodulated sequence from the second number of digits per sample into a decompressed sequence having the first number of digits per sample, and (iii) decode the decompressed sequence.

A data translation system (100) for performing a non-linear data translation on a digitized AC signal is provided. The non-linear data translation system (100) includes an input for receiving the digitized AC signal, an output for outputting a non-linearly translated signal, and a processing system (104) coupled to the input and to the output. The processing system (104) is configured to receive the digitized AC signal, non-linearly translate the digitized AC signal using a predetermined transfer function to create the non-linearly translated signal, and transfer the non-linearly translated signal to the output.

An electronic circuit comprises an analog-to-digital converter (ADC) circuit. The ADC circuit includes a pre-amplifying transistor and a quantizer circuit. The pre-amplifying transistor includes a base, an emitter and a collector. The pre-amplifying transistor is configured to receive an input voltage at the base that varies logarithmically; and produce an output voltage at the collector according to a comparison of a reference voltage and a difference between the input voltage and a voltage at the emitter. The quantizer circuit is operatively coupled to the pre-amplifying transistor and is configured to generate a digital value for the input voltage using the output voltage produced by the pre-amplifying transistor.

An optical network includes a transmitting portion configured to (i) encode an input digitized sequence of data samples into a quantized sequence of data samples having a first number of digits per sample, (ii) map the quantized sequence of data samples into a compressed sequence of data samples having a second number of digits per sample, the second number being lower than the first number, and (iii) modulate the compressed sequence of data samples and transmit the modulated sequence over a digital optical link. The optical network further includes a receiving portion configured to (i) receive and demodulate the modulated sequence from the digital optical link, (ii) map the demodulated sequence from the second number of digits per sample into a decompressed sequence having the first number of digits per sample, and (iii) decode the decompressed sequence.

An electronic circuit comprises an analog-to-digital converter (ADC) circuit. The ADC circuit includes a pre-amplifying transistor and a quantizer circuit. The pre-amplifying transistor includes a base, an emitter and a collector. The pre-amplifying transistor is configured to receive an input voltage at the base that varies logarithmically; and produce an output voltage at the collector according to a comparison of a reference voltage and a difference between the input voltage and a voltage at the emitter. The quantizer circuit is operatively coupled to the pre-amplifying transistor and is configured to generate a digital value for the input voltage using the output voltage produced by the pre-amplifying transistor.

An analog signal processing circuit comprising: a first promoter operably linked to a nucleic acid sequence encoding a first output molecule, wherein said promoter is responsive to a cooperative input signal comprising at least two cooperative inputs, and wherein expression of said at least two cooperative inputs is tunable.

An optical network includes a transmitting portion configured to (i) encode an input digitized sequence of data samples into a quantized sequence of data samples having a first number of digits per sample, (ii) map the quantized sequence of data samples into a compressed sequence of data samples having a second number of digits per sample, the second number being lower than the first number, and (iii) modulate the compressed sequence of data samples and transmit the modulated sequence over a digital optical link. The optical network further includes a receiving portion configured to (i) receive and demodulate the modulated sequence from the digital optical link, (ii) map the demodulated sequence from the second number of digits per sample into a decompressed sequence having the first number of digits per sample, and (iii) decode the decompressed sequence.

The circuit device includes an integration period signal generation circuit, a polarity switching signal generation circuit, and first and second integration circuits. The integration period signal generation circuit generates a first integration period signal kept in an active state in the first integration period. The polarity switching signal generation circuit generates a first integration polarity switching signal making a transition at a timing synchronized with the reference clock signal in the first integration period, and a second integration polarity switching signal making a transition a predetermined clock count of the reference clock signal after the transition timing of the first integration polarity switching signal in the first integration period. The first integration circuit performs an integrating process in which an integration polarity is switched at the transition timing of the first integration polarity switching signal in the first integration period. The second integration circuit performs an integrating process in which an integration polarity is switched at the transition timing of the second integration polarity switching signal in the first integration period.

A method of signal processing for handling a digital signal outputted by an analog-to-digital converter includes determining a candidate interval corresponding to each of multiple sampling points in a sampling space of the digital signal, wherein the candidate interval is one of multiple candidate intervals, calculating numbers of sampling points corresponding to each one of the multiple candidate intervals to determine a delegate candidate interval, and calculating a delegate value of the sampling space according to a number of sampling points corresponding to the delegate candidate interval and values of the sampling points corresponding to the delegate candidate interval.