H03M1/124

RECEIVER WITH PIPELINE STRUCTURE FOR RECEIVING MULTI-LEVEL SIGNAL AND MEMORY DEVICE INCLUDING THE SAME

A receiver receiving a multi-level signal includes a sample and hold circuit, first and second analog-to-digital converting circuits, and a digital-to-analog converting circuit. The sample and hold circuit generates a sample data signal by sampling and holding an input data signal. The first analog-to-digital converting circuit generates a first bit of output data based on the input data signal and a first selection reference voltage among a plurality of reference voltages. The digital-to-analog converting circuit selects at least one additional selection reference voltage from among the plurality of reference voltages based on the first bit of the output data. The second analog-to-digital converting circuit generates at least one additional bit of the output data based on the sample data signal and the at least one additional selection reference voltage.

DEVICES, SYSTEMS, AND METHODS FOR TIME CORRECTION

The present disclosure provides devices, systems, and methods for time correction. The device may include a first time measurement component configured to measure a receiving time of a valid signal; a correction component configured to collect correction information for correcting the receiving time of the valid signal; and a processing device configured to determine a corrected receiving time of the valid signal by correcting the receiving time of the valid signal based on the correction information.

NOISE REDUCING CAPACITANCE DRIVER
20220337264 · 2022-10-20 ·

A circuit having a capacitance driver circuit can allow for reduction of thermal noise to an application circuit. An output of the capacitance driver circuit can drive a capacitor for use by the application circuit coupled to the capacitor at the output of the capacitance driver circuit. The capacitance driver circuit can be structured to operate over a bandwidth of interest. With an input signal, received at the capacitance driver circuit, associated with a target voltage, an output voltage can be provided at the output of the capacitance driver circuit as a bandlimited filtered voltage value of the target voltage, where a root-mean-square voltage deviation of the output voltage from the target voltage, due to thermal noise, is less than a square root of (kT/C). The term k is Boltzmann's constant, T is Kelvin temperature of the capacitance driver circuit, and C is the capacitance of the driven capacitor.

Pre-drive module of analog-to-digital converter, and analog-to-digital conversion device

Disclosed are a pre-drive module of an analog-to-digital converter and an analog-to-digital conversion device. The pre-drive module includes a sampling capacitor; a controller configured to output a reset control signal, a pre-sampling control signal, and a sampling control signal according to a preset timing sequence; a reset module configured to reset the sampling capacitor upon receiving the reset control signal; a first auxiliary drive circuit configured to amplify an input analog signal and output to the sampling capacitor for sampling upon receiving the sample control signal; and a second auxiliary drive circuit. The controller is configured to output the pre-sampling control signal before outputting the sampling control signal, control the second auxiliary drive circuit to amplify the input analog signal, and output to the sampling capacitor for pre-sampling, and when a charging voltage of the sampling capacitor during pre-sampling reaches a preset voltage value, output the sampling control signal.

Track-And-Hold Circuit
20230155600 · 2023-05-18 ·

Bias adjusting circuits (1_(2k-1), 1_2k) (where k is an integer equal to or greater than 1 and equal to or less than N, and N is an integer equal to or more than .sub.2) adjust DC bias voltage of at least one of clock signals such that a duty ratio, which is a ratio between a period in which a clock signal is High as to a clock signal and a period in which the clock signal is Low thereasto, becomes (2N-2k+1):(2k-1). Sampling circuits switch between a track mode in which an output signal tracks an input signal, and a hold mode in which a value of the input signal at a timing of switching from the track mode to the hold mode is held and output, in accordance with clock signals output from the bias adjusting circuits (2_1 to 2_2N).

Amplification interface, and corresponding measurement system and method for calibrating an amplification interface

A thermally-isolated-metal-oxide-semiconducting (TMOS) sensor has inputs coupled to first and second nodes to receive first and second bias currents, and an output coupled to a third node. A tail has a first conduction terminal coupled to the third node and a second conduction terminal coupled to a reference voltage. A control circuit applies a control signal to a control terminal of the tail transistor based upon voltages at the first and second nodes so that a common mode voltage at the first and second nodes is equal to a reference common mode voltage. A differential current integrator has a first input terminal coupled to the second node and a second input terminal coupled to the first node, and provides an output voltage indicative of an integral of a difference between a first output current at the first input terminal and a second output current at the second input terminal.

Switched Emitter Follower Circuit
20230141476 · 2023-05-11 ·

A switched emitter follower circuit is constituted by a transistor in which a base is connected to a signal input terminal, a power voltage is applied to a collector, and an emitter is connected to a signal output terminal, a capacitor in which one end is connected to the collector of the transistor, and the other end is connected to the emitter of the transistor, and a Gilbert-cell type multiplication circuit in which a positive-phase clock output terminal is connected to the emitter of the transistor, a negative-phase clock output terminal is connected to the base of the transistor, and a multiplication result of a differential clock signal and a differential clock signal input from an outside is output to the positive-phase clock output terminal and the negative-phase clock output terminal.

Discrete offset dithered waveform averaging for high-fidelity digitization of repetitive signals

Methods and devices for digitizing an analog repetitive signal using waveform averaging are described. An example method includes generating a discrete set of analog dither offset voltages, wherein at least two of the discrete set of analog dither offset voltages are different from each other, receiving the analog repetitive signal comprising multiple instances of a waveform, wherein the waveform has a waveform duration, generate a timing alignment to align each waveform of the analog repetitive signal and the corresponding analog dither offset voltage over the waveform duration, combining, based on the timing alignment, each waveform and the corresponding analog dither offset voltage over the waveform duration to produce an analog output signal, converting the analog output signal to a digital output signal, and producing, based on the timing alignment, a digital averaged signal based on averaging the multiple instances of the waveform in the analog output signal.

COMPARATOR, AD CONVERTER, PHOTOELECTRIC CONVERSION DEVICE, IMAGING SYSTEM, AND MOVABLE OBJECT
20230132676 · 2023-05-04 ·

A disclosed comparator includes a comparison circuit including a differential unit that compares an input signal with a reference signal and changes a level of a signal output to a first node in accordance with a result of comparison and an amplifier unit that includes a load element and outputs a signal in accordance with a potential of the first node to a second node, and a positive feedback circuit that is connected to the second node and a third node and changes a level of a signal at the third node at a rate higher than a change rate of a level of a signal at the second node in accordance with a change in a level of a signal at the second node.

CROSS SPECTRUM ANALYSIS FOR TIME STAMPED SIGNALS
20230204791 · 2023-06-29 · ·

For cross-channel spectral analysis of measurement data from multiple recording units with independent sampling clocks, a processing method corrects phase mismatch between the data received over the different channels. Blocks of sampled measurement data are buffered in a hardware logic circuit and timestamps are associated with successive blocks through a hardware interrupt to a GPS receiver of each recording unit. For each first channel data block, the block's starting point, a closest point in time in a data block of the second channel, and the starting point of that second channel data block are determined, using GPS timestamps associated with those data blocks, nominal sampling rate and block size. Phase correction based on the time offset between starting points of the pairs of data blocks and the interval between starting points of successive blocks is applied in the frequency domain after a time-to-frequency domain transformation. Multiple frames of phase-corrected spectra may then be averaged. Only a subset of samples in each data block need be used based upon a specified overlap ratio.