An analog-to-digital converter (ADC) includes a first ADC stage with a first sub-ADC stage configured to sample the analog input voltage in response to a first phase clock signal and output a first digital value corresponding to an analog input voltage in response to a second phase clock signal. A current mode DAC stage is configured to convert the analog input voltage and the first digital value to respective first and second current signals, determine a residue current signal representing a difference between the first and the second current signal, and convert the residue current signal to an analog residual voltage signal. A second ADC stage is coupled to the first ADC stage to receive the analog residual voltage signal, and convert the analog residue voltage signal to a second digital value. An alignment and digital error correction stage is configured to combine the first and the second digital values.

An apparatus configured to convert an analog input signal into a digital output signal may include a first amplification circuit configured to receive the analog input signal and a plurality of reference voltages and amplify differences between the analog input signal and the plurality of reference voltages; a plurality of first capacitors configured to respectively store charges corresponding to signals outputted by the first amplification circuit; a second amplification circuit configured to amplify differences among voltages of the plurality of first capacitors; a plurality of second capacitors configured to respectively store charges corresponding to signals outputted by the second amplification circuit; and a comparison circuit configured to generate the digital output signal by comparing voltages of the plurality of second capacitors with each other.

An asynchronous capacitance-to-digital converter (CDC) is described that allows for very low-power operation when during inactive periods (when no conductive object is in contact or proximity to the sensing electrodes). Asynchronous operation of the CDC provides for capacitance-to-digital conversion without the use of system resources and more power intensive circuit elements.

An asynchronous capacitance-to-digital converter (CDC) is described that allows for very low-power operation when during inactive periods (when no conductive object is in contact or proximity to the sensing electrodes). Asynchronous operation of the CDC provides for capacitance-to-digital conversion without the use of system resources and more power intensive circuit elements.

A multiply-accumulate (MAC) computation circuit includes: a bit-cell array configured to generate an analog output corresponding to a MAC operation result of an input signal; a first analog-to-digital conversion (ADC) circuit configured to determine an upper part of a digital output corresponding to the analog output; and a second ADC circuit configured to determine a lower part of the digital output based on a reference voltage corresponding to the upper part.

Disclosed is a circuit which includes a first amplifier that generates a first output signal by comparing a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operating period and comparing the ramp signal and an image signal of the pixel signal output from the pixel array in a second operating period, a second amplifier that generates a second output signal based on the first output signal, and a counter. During at least one operating period of the first operating period and the second operating period, the first output signal controls a first source current of the first amplifier, or the second output signal controls at least one of the first source current of the first amplifier and a second source current of the second amplifier.

Disclosed is a circuit which includes a first amplifier that generates a first output signal by comparing a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operating period and comparing the ramp signal and an image signal of the pixel signal output from the pixel array in a second operating period, a second amplifier that generates a second output signal based on the first output signal, and a counter. During at least one operating period of the first operating period and the second operating period, the first output signal controls a first source current of the first amplifier, or the second output signal controls at least one of the first source current of the first amplifier and a second source current of the second amplifier.

An integrating Analog-to-digital converter has a global counter that outputs a counter code signal including a multiphase signal. It also has a column circuit including: a ramp wave generation circuit outputting a ramp wave voltage; a comparator comparing the ramp wave voltage with a pixel voltage; and a latch circuit latching the counter code signal at output inversion timing of the comparator. An output value of the latch circuit is used as a digital conversion output value per the column circuit. The counter has a phase division circuit outputting, as an LSB of the digital conversion output value of the integrating analog-to-digital converter, a phase division signal to the latch circuit, the phase division signal dividing a phase of the counter code signal. The phase division circuit is arranged to a plurality of column circuits, and the LSB is shared by a plurality of phase division circuits.

Disclosed is a circuit which includes a first amplifier that generates a first output signal by comparing a ramp signal and a reset signal of a pixel signal output from a pixel array in a first operating period and comparing the ramp signal and an image signal of the pixel signal output from the pixel array in a second operating period, a second amplifier that generates a second output signal based on the first output signal, and a counter. During at least one operating period of the first operating period and the second operating period, the first output signal controls a first source current of the first amplifier, or the second output signal controls at least one of the first source current of the first amplifier and a second source current of the second amplifier.

An integrator and an analog-to-digital converter are provided. The analog-to-digital converter includes the integrator, a comparison circuit and a control logic circuit. The integrator includes an operational amplifier, offset capacitors, input capacitors, integral capacitors and controllable switches. The input capacitors and the integral capacitors are connected to the operational amplifier via controllable switches, so that the integrator operates in various operation modes. Operation states of the offset capacitors in a first phase and a second phase of an operation cycle are controlled by switching on or off the controllable switches. Therefore, an offset voltage of the integrator is eliminated, and conversion efficiency and conversion accuracy of the analog-to-digital converter is improved.