Methods and architectures for refreshing memory elements in a memory array may initialize a reference array that stores each of the possible values stored in the memory element. The values in the memory array and the reference array will drift in parallel over time. To perform a refresh, the drifted values may be read from the reference array and mapped to the original values that were stored when the reference array was initialized. Next, each value may be read from the memory array and matched with a corresponding value from the reference array. The known original value stored in the reference array can then be used to refresh the corresponding memory element in the memory array.

An analog-to-digital converter is disclosed that converts an input analog potential to a digital conversion value. An analog-to-digital converter according to one or more embodiments may include a comparator that compares the input analog potential with a reference potential; and a conversion circuit that measures comparison operation time from a start to an end of a comparison operation by the comparator and outputs the digital conversion value according to the measured comparison operation time and a comparison result by the comparator.

A data acquisition system comprises a signal processing chain including an analog-to-digital converter (ADC) circuit configured to: produce a digital output from an input signal; detect a specified signal feature of the input signal; and change an operating condition of an additional circuit of the signal processing chain in response to detecting the signal feature of the input signal.

A data acquisition system comprises a signal processing chain including an analog-to-digital converter (ADC) circuit configured to: produce a digital output from an input signal; detect a specified signal feature of the input signal; and change an operating condition of an additional circuit of the signal processing chain in response to detecting the signal feature of the input signal.

An asynchronous capacitance-to-digital conversion is described that allows for very low-power operation when during inactive periods (when no conductive object is in contact or proximity to the sensing electrodes). Asynchronous operation of a capacitance-to-digital converter (CDC) provides for capacitance-to-digital conversion without the use of system resources and more power intensive circuit elements.

An asynchronous capacitance-to-digital conversion is described that allows for very low-power operation when during inactive periods (when no conductive object is in contact or proximity to the sensing electrodes). Asynchronous operation of a capacitance-to-digital converter (CDC) provides for capacitance-to-digital conversion without the use of system resources and more power intensive circuit elements.

In an analog-to-digital converter circuit, a sum output unit calculates the sum of an n-bit data value outputted from a first output unit and an (n + 1)-bit data value outputted from a second output unit to accordingly obtain the calculated sum as a digital data value. A second calculator of the second output unit calculates the sum of a sign bit of a third digital data value as a most significant bit thereof and a second significant bit of the third digital data value. The combines a bit selected from the calculated sum with the third digital data value from which the sign bit has been eliminated to accordingly generate, as the (n + 1)-bit data value, a new digital data value whose most significant bit is the bit selected from the calculated sum.

An analog-to-digital conversion method, an analog-to-digital converter and an image sensor, are provided. The analog-to-digital conversion method includes a first conversion period and a second conversion period; in the first conversion period and the second conversion period, a first counter and the second counter have different effective clock edges and work in a time-sharing way using the first count clock signal and the second count clock signal respectively; in the second conversion period, count directions of the first counter and the second counter are reversed, and the count results in the first conversion period are used as an initial value of the second conversion period; and the conversion result is output based on the first count result and the second count result.

A mixed-signal integrated circuit that includes: a global reference signal source; a first summation node and a second summation node; a plurality of distinct pairs of current generating circuits arranged along the first summation node and the second summation node; a first current generating circuit of each of the plurality of distinct pairs that is arranged on the first summation node and a second current generating circuit of each of the plurality of distinct pairs is arranged on the second summation node; a common-mode current circuit that is arranged in electrical communication with each of the first and second summation nodes; where a local DAC adjusts a differential current between the first second summation nodes based on reference signals from the global reference source; and a comparator or a finite state machine that generates a binary output value current values obtained from the first and second summation nodes.

Methods and architectures for refreshing memory elements in a memory array may initialize a reference array that stores each of the possible values stored in the memory element. The values in the memory array and the reference array will drift in parallel over time. To perform a refresh, the drifted values may be read from the reference array and mapped to the original values that were stored when the reference array was initialized. Next, each value may be read from the memory array and matched with a corresponding value from the reference array. The known original value stored in the reference array can then be used to refresh the corresponding memory element in the memory array.