An analog-to-digital converter (ADC) includes a first comparator configured to generate a first comparison signal on a basis of a first asynchronous clock signal generated from a sampling clock signal, and a second comparator configured to generate a second comparison signal on a basis of a second asynchronous clock signal generated by a first comparison operation completion signal. The ADC includes a first control logic configured to output a first control signal on a basis of the first comparison signal and a second control logic configured to output a second control signal on a basis of the second comparison signal. The ADC includes a first reference signal adjusting circuit configured to adjust a first reference signal on a basis of the first control signal and a second reference signal adjusting circuit configured to adjust a second reference signal on a basis of the second control signal.

Systems, apparatuses and methods may provide for compute-in-memory (CiM) accelerator technology that includes a multiply-accumulate (MAC) computation stage, an analog amplifier stage coupled to an output of the MAC computation stage, and an analog to digital conversion (ADC) stage coupled to an output of the analog amplifier stage, wherein a gain setting of the analog amplifier stage modifies a quantization granularity of the ADC stage.

Systems, apparatuses and methods may provide for compute-in-memory (CiM) accelerator technology that includes a multiply-accumulate (MAC) computation stage, an analog amplifier stage coupled to an output of the MAC computation stage, and an analog to digital conversion (ADC) stage coupled to an output of the analog amplifier stage, wherein a gain setting of the analog amplifier stage modifies a quantization granularity of the ADC stage.

Apparatus includes an ADC configured to convert an analog signal to a digital signal, a comparator having a first input responsive to the analog signal, a second input responsive to the digital signal, and an output at which a comparison signal is provided, and an output checker configured to process the comparison signal to generate a fault signal indicative of whether a fault has occurred in the ADC. The comparator can be an analog comparator in which case the digital signal is converted to an analog signal for the comparison or a digital comparator in which case an additional ADC is provided to convert the analog signal into a digital signal for the comparison. Embodiments include more than one ADC in which case summation elements are provided to sum the analog signals and the digital signals for the comparison.

Provided is an analog to digital converter configured to receive a continuous input signal. The analog to digital converter includes an integrating block, comprising at least an integrating stage, which output is coupled to a flash analog to digital converter. The analog to digital converter apparatus includes a feedback path coupled to the output of said flash analog to digital converter. The feedback path includes at least a digital to analog conversion block which output is compared at least to the input signal to obtain an error signal which is brought as input to said integrating block. A control block is configured to perform control comprising at least a digital integration, is coupled between the output of said flash analog to digital converter and said feedback path.

An apparatus configured to convert an analog input signal into a digital output signal may include a first amplification circuit configured to receive the analog input signal and a plurality of reference voltages and amplify differences between the analog input signal and the plurality of reference voltages; a plurality of first capacitors configured to respectively store charges corresponding to signals outputted by the first amplification circuit; a second amplification circuit configured to amplify differences among voltages of the plurality of first capacitors; a plurality of second capacitors configured to respectively store charges corresponding to signals outputted by the second amplification circuit; and a comparison circuit configured to generate the digital output signal by comparing voltages of the plurality of second capacitors with each other.

A measurement system includes a gain chain configured to amplify an analog input signal; a range selector configured to select a gain between the analog input signal and a plurality of analog-to-digital converter (ADC) outputs from a plurality of ADCs, wherein each ADC output has a path, and a gain of each output path is made up of a plurality of gain stages in the gain chain; and a mixer configured to combine the plurality of ADC outputs into a single mixed output.

A feed forward equalizer including a first set of filter taps having a first set of filter tap coefficients to be adapted and a second set of one or more filter taps having one or more filter tap coefficients to be constrained. The feed forward equalizer includes an adaptation component to determine a set of adapted filter tap coefficient values corresponding to the first set of filter tap coefficients and a constraint function component to determine a constrained filter tap coefficient value for the second set of the one or more filter taps having the one or more filter tap coefficients to be constrained using a constraint function based on at least a portion of the set of adapted filter tap coefficient values. The feed forward equalizer generates, based at least in part on the constrained filter tap coefficient value, an equalized signal including a set of estimated symbol values.

A processing device is provided. The processing device comprises one or more interfaces configured to transmit information to a nonlinear device and processing circuitry configured to control the one or more interfaces and to. Further, the processing circuitry is configured to transmit an excitation signal to the nonlinear device and to receive response information from the nonlinear device. Further, the processing circuitry is configured to determine a linear response of the nonlinear device based on the response information and to determine a nonlinear response of the nonlinear device based on the determined linear response.

A circuit includes an operational amplifier and a resistor network coupled to an output of the operational amplifier. The resistor network includes a first set of resistors coupled between the output of the operational amplifier and a first node of the resistor network, wherein the resistors of the first set are electrically connected in series with each other, a second set of resistors coupled between the first node and a second node of the resistor network, wherein the resistors of the second set are electrically connected in series with each other and include a first number of resistors, a third set of resistors coupled between the second node and a third node of the resistor network, wherein the third node is coupled to a first voltage, and wherein the resistors of the third set are electrically connected in parallel with each other and include a second number of resistors, and a resistor coupled between the first node and the second node and arranged in parallel with the second set of resistors.