Methods and devices for digitizing an analog repetitive signal using waveform averaging are described. An example method includes generating a time-varying dither signal, receiving the analog repetitive signal comprising multiple instances of a waveform, wherein each waveform has a waveform duration, wherein an average of the time-varying dither signal over multiple waveform durations is substantially zero, and wherein the time-varying dither signal varies over each waveform duration, generating a timing alignment, combining each waveform with the corresponding portion of the time-varying dither signal over each waveform duration to produce an analog output signal, converting the analog output signal to a digital output signal, and producing, based on the timing alignment, a digital averaged signal based on averaging the multiple instances of the waveform in the analog output signal, wherein the timing alignment is used to align the multiple instances of the waveform in the analog output signal.

This disclosure describes techniques for transferring data from an analog-to-digital converter (ADC) to a host device. The techniques may determine whether an ADC is operating in a quiet conversion time period, and selectively deactivate a digital data output of the ADC when the ADC is operating in the quiet conversion time period. This may allow an ADC to transfer data during both the conversion and acquisition phases of the ADC (rather than just during the acquisition phase), thereby increasing the data throughput of the ADC for a given transfer clock speed. The techniques may further allow data to be transferred during the conversion phase of an ADC without requiring a host device to be aware of the quiet conversion time period requirements of the ADC. In this way, the data throughput of an ADC data transfer may be increased with relatively little additional complexity added to a host device.

This disclosure describes techniques for transferring data from an analog-to-digital converter (ADC) to a host device. The techniques may determine whether an ADC is operating in a quiet conversion time period, and selectively deactivate a digital data output of the ADC when the ADC is operating in the quiet conversion time period. This may allow an ADC to transfer data during both the conversion and acquisition phases of the ADC (rather than just during the acquisition phase), thereby increasing the data throughput of the ADC for a given transfer clock speed. The techniques may further allow data to be transferred during the conversion phase of an ADC without requiring a host device to be aware of the quiet conversion time period requirements of the ADC. In this way, the data throughput of an ADC data transfer may be increased with relatively little additional complexity added to a host device.

Methods and apparatus disclosed herein implement or otherwise embody a technique that compensates for cyclic position errors in encoder-based position detection, wherein the cyclic position errors arise from the presence of harmonic components in the encoder signals relied upon for position determination. Using position-domain compensation for errors arising in the encoder domain offers computational simplicity and impressive compensation performance, even when compensating for a plurality of higher harmonics in the encoder signals, e.g., third harmonic, fifth harmonic, etc. Consequently, even high-precision position monitoring or control can use relatively inexpensive types of encoders known to output encoder signals having significant harmonic components.

A flash analog to digital converter includes a voltage generator circuit, an encoder circuit, and first and second double differential amplifier circuits. The voltage generator circuit generates reference voltages according to first and second voltages. The encoder circuit generates a digital signal corresponding to an input signal according to first signals. The first double differential amplifier circuit compares the input signal with a first reference voltage in the reference voltages, to generate a corresponding one of the first signals. The second double differential amplifier circuit compares the input signal with a second reference voltage in the reference voltages, to generate a corresponding one of the first signals. A difference between the first voltage and the first reference voltage is less than that between the first voltage and the second reference voltage, and the first and the second double differential amplifier circuits have different circuit architectures.

A device for true random number generation is disclosed. The device comprises an antenna and an analog processing unit for analog processing of a signal received from the antenna. An analog to digital (AD) converter is used for converting an analog signal generated by the analog processing unit into a digital signal. An isolation means is applied for temporarily isolating the antenna from the analog processing unit and the AD converter to generate a noise signal. A sampling means is used for sampling output values generated by the AD converter when the antenna is isolated from the analog processing unit and the AD converter. A digital processing unit is used for processing the sampled output values generated by the AD converter. The digital processing unit is configured to generate a random number based on one or more of the output values generated by the AD converter.

A charge rebalancing integration circuit can help keep an output node of a front-end integration circuit within a specified range, e.g., without requiring resetting of the integration capacitor. The process of monitoring and rebalancing the integration circuit can operate on a much shorter time base than the integration time period, which can allow for multiple charge balancing charge transfer events during the integration time period, and sampling of the integration capacitor once per integration time period, such as at the end of that integration time period. Information about the charge rebalancing can be used to adjust subsequent discrete-time signal processing, such as digitized values of the samples. Improved dynamic range and noise performance is possible. Computed tomography (CT) imaging and other use cases are described, including those with variable integration periods.

A capacitive sensing system operates according to a method which uses an ADC. The analog signal to be digitized is modulated with a triangular or saw-tooth modulating signal, so that a modulated analog signal is obtained, which is sampled with the ADC. The triangular or saw-tooth signal is chosen to have a peak-to-peak amplitude corresponding at least approximately to an integer multiple L, with L≥1, of the quantization step size of the ADC. The saw-tooth or triangular signal has a number M, of periods per each sequence of N samples. M and N are chosen such that M>1 and M≠N and such that R=r*N/(k*gcd(N, M)*L), where gcd(M, N) is the greatest common divisor of N and M and where k=2 if the modulating signal is a saw-tooth signal and k=4 if the modulating signal is a triangular signal.

A capacitive sensing system operates according to a method which uses an ADC. The analog signal to be digitized is modulated with a triangular or saw-tooth modulating signal, so that a modulated analog signal is obtained, which is sampled with the ADC. The triangular or saw-tooth signal is chosen to have a peak-to-peak amplitude corresponding at least approximately to an integer multiple L, with L≥1, of the quantization step size of the ADC. The saw-tooth or triangular signal has a number M, of periods per each sequence of N samples. M and N are chosen such that M>1 and M≠N and such that R=r*N/(k*gcd(N, M)*L), where gcd(M, N) is the greatest common divisor of N and M and where k=2 if the modulating signal is a saw-tooth signal and k=4 if the modulating signal is a triangular signal.

An analog-to-digital converter that converts an inputted analog signal into a digital value is disclosed that may include unit circuits that each generate reference voltages comprising regular potential intervals by a series resistor circuit connected between a high potential side reference voltage and a low potential side reference voltage and convert the reference voltages into a digital value by comparing the reference voltages with the inputted analog signal, and an adder that adds the digital values converted by the unit circuits. Each unit circuit may include coupling switches that couple the series resistor circuit with the series resistor circuit of another one of the unit circuits and connect the series resistor circuits between the high potential side reference voltage and the low potential side reference voltage and a sharing switch that shares the inputted analog signal with the other unit circuit that is coupled with the series resistor circuit.