An analog-to-digital converter that converts an inputted analog signal into a digital value is disclosed that may include unit circuits that each generate reference voltages comprising regular potential intervals by a series resistor circuit connected between a high potential side reference voltage and a low potential side reference voltage and convert the reference voltages into a digital value by comparing the reference voltages with the inputted analog signal, and an adder that adds the digital values converted by the unit circuits. Each unit circuit may include coupling switches that couple the series resistor circuit with the series resistor circuit of another one of the unit circuits and connect the series resistor circuits between the high potential side reference voltage and the low potential side reference voltage and a sharing switch that shares the inputted analog signal with the other unit circuit that is coupled with the series resistor circuit.

A circuit device includes a clock generation circuit, a signal generation circuit, a phase comparison circuit, and a processing circuit. The signal generation circuit generates a first signal making the transition at a transition timing of a first clock signal, a fine-judging signal making the transition at a transition timing of a second clock signal, a first coarse-judging signal making the transition at a transition timing of the second clock signal anterior to the fine-judging signal, and a second coarse-judging signal making the transition at a transition timing of the second clock signal posterior to the fine-judging signal. The phase comparison circuit performs the phase comparison between the second signal making the transition based on the first signal and each of the fine-judging signal, the first coarse-judging signal, and the second coarse-judging signal. The processing circuit sets the transition timing of the first signal and the transition timing of the fine-judging signal based on the phase comparison result, and converts a time difference between the first signal and the second signal into a digital value based on the setting result.

A sensor device includes an A/D converter including an adder that computes a difference between an analog input signal and a predicted value, the adder includes a capacitive adder defined by a series circuit including a capacitive charge output device and a capacitor. A capacitive component in the charge output device defines a portion of the capacitance of the capacitive adder. A digital prediction filter generates the predicted value based on an output from a quantizer. The capacitive adder computes the difference between the analog input signal from the charge output device and the predicted value. The quantizer quantizes and encodes the difference. The A/D converter performs a Δ modulation on the analog input signal which is converted into a digital signal.

An image sensor may contain an array of imaging pixels. Each pixel column outputs signals that are read out using a successive approximation register (SAR) analog-to-digital converter (ADC). The SAR ADC may include at least first and second input sampling capacitors, a comparator, a capacitive digital-to-analog converter (CDAC), and associated control circuitry. If desired, the SAR ADC may include a bank of more than two input sampling capacitors alternating between sampling and conversion. The first capacitor may be used to sample an input signal while conversion for the second capacitor is taking place. Prior to conversion, an input voltage of the comparator and an output voltage of the CDAC may be initialized. During conversion of the signal on the first capacitor, the first capacitor is embedded within the SAR ADC feedback loop to prevent charge sharing between the input sampling capacitor and the CDAC, thereby mitigating potential capacitor mismatch issues.

A digital signal generation assumes that a base frequency (the frequency with which the primitive phase angles are specified relative to) is equal to the carrier frequency for all relevant times. But this causes errors in the digital signals output to each array element transducer. Thus, it is necessary for the development of a signal generation system that is capable of producing a digital signal using the free selection of amplitude and phase. This is used to produce a substantially error-free signal that preserves the amplitude and phase relative to a constant base frequency while allowing the carrier frequency to vary.

A system for converting a voltage into output codes includes logic gates for processing delay signals based on earlier and later arriving signals generated by preamplifiers, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits of the codes, and an auxiliary delay comparator for generating an auxiliary digital signal for use in generating the output codes. A system may include logic gates for generating delay signals based on earlier and later arriving signals, delay comparators for generating digital signals representative of most significant bits of respective codes, and for transmitting delay residue signals representative of less significant bits, and a multiplexer system for transmitting a selected one of the residue signals.

Aspects relate to analog-to-digital conversion of an analog signal. The resolution (number of bits) and/or the quantization levels of the analog-to-digital conversion may be configurable. A device may configure its analog-to-digital conversion parameters. For example, a first device may reduce the number of bits for its analog-to-digital converter to reduce power consumption. In this case, the first device may transmit an indication of selected analog-to-digital conversion parameters to a second device that will transmit to the first device. In this way, the second device may take appropriate action, if needed. A device may request another device to use certain analog-to-digital conversion parameters. For example, a first device may determine that a second device should use a larger number of bits for its analog-to-digital conversion process to improve the quality of the communication between the first and second devices.

Aspects relate to analog-to-digital conversion of an analog signal. The resolution (number of bits) and/or the quantization levels of the analog-to-digital conversion may be configurable. A device may configure its analog-to-digital conversion parameters. For example, a first device may reduce the number of bits for its analog-to-digital converter to reduce power consumption. In this case, the first device may transmit an indication of selected analog-to-digital conversion parameters to a second device that will transmit to the first device. In this way, the second device may take appropriate action, if needed. A device may request another device to use certain analog-to-digital conversion parameters. For example, a first device may determine that a second device should use a larger number of bits for its analog-to-digital conversion process to improve the quality of the communication between the first and second devices.

Methods, systems, and devices for wireless communication are described for one or more aspects of dynamically configuring an analog-to-digital converter (ADC). A user equipment (UE) may determine a set of supported ADC resolution sizes including one or more dynamically configurable bit quantities. The UE may transmit a capability message including an indication of the set of ADC resolution sizes to a base station. The UE may indicate, to the base station, a power consumption factor or a table of signal-to-quantization noise ratios (SQNR) per bit quantity supported by the UE's ADC. In some cases, the base station may enable, based on the set of ADC resolution sizes, clipping of a power amplifier and one or more associated precoding parameters, and may indicate the precoding parameters to the UE. The UE may select an ADC resolution size for processing received messages.

Methods, systems, and devices for wireless communication are described for one or more aspects of dynamically configuring an analog-to-digital converter (ADC). A user equipment (UE) may determine a set of supported ADC resolution sizes including one or more dynamically configurable bit quantities. The UE may transmit a capability message including an indication of the set of ADC resolution sizes to a base station. The UE may indicate, to the base station, a power consumption factor or a table of signal-to-quantization noise ratios (SQNR) per bit quantity supported by the UE's ADC. In some cases, the base station may enable, based on the set of ADC resolution sizes, clipping of a power amplifier and one or more associated precoding parameters, and may indicate the precoding parameters to the UE. The UE may select an ADC resolution size for processing received messages.