Systems and methods of implementing a mixed-signal integrated circuit includes sourcing, by a reference signal source, a plurality of analog reference signals along a shared signal communication path to a plurality of local accumulators; producing an electrical charge, at each of the plurality of local accumulators, based on each of the plurality of analog reference signals; adding or subtracting, by each of the plurality of local accumulators, the electrical charge to an energy storage device of each of the plurality of local accumulators over a predetermined period; summing along the shared communication path the electrical charge from the energy storage device of each of the plurality of local accumulators at an end of the predetermined period; and generating an output based on a sum of the electrical charge from each of the plurality of local accumulators.

A pipeline analog to digital converter includes converter circuitries and a calibration circuitry. The converter circuitries sequentially convert an input signal into first digital codes. A first converter circuitry in the converter circuitries performs a quantization according to a first signal to generate a first corresponding digital code in the first digital codes, and the first signal is a signal, which is processed by the first converter circuitry, of the input signal and a previous stage residue signal. The calibration circuitry combines the first digital codes to output a second digital code, detects whether the quantization is completed to generate first and second valid signals, and determines whether to set the second digital code to be a first predetermined digital code or a second predetermined digital code according to the first and the second valid signals. The second valid signal is a delay signal of the first valid signal.

A tracking analog-to-digital converter (ADC) for a power converter includes a first tracking loop and a second tracking loop. The first tracking loop is configured to track a voltage input to the tracking ADC using one or more comparators and has a re-clocking circuit to mitigate the impact of comparator output metastability, but introduces multi-cycle latency which increases a residual error of the voltage tracking provided by the first tracking loop. The second tracking loop is configured to supplement the voltage tracking provided by the first tracking loop and to reduce the residual error of the voltage tracking for dynamic changes at the voltage input. The second tracking loop has a single-cycle latency and is implemented with logic that is less sensitive to logic errors due to comparator metastability. Corresponding methods of voltage tracking and an electronic system are also described.

An analog to digital converter (ADC) comprising: a delay circuit having a complementary signal output; a first comparator having an input coupled to the complementary signal output of the delay circuit, the first comparator having a first output and a second output; a first dummy comparator having a first dummy input coupled to the first output and a second dummy input coupled to the second output, the first dummy comparator having a dummy output; a first interpolation comparator having an interpolation output and a first interpolation input coupled to the first output; a second dummy comparator having an input coupled to the interpolation output; and a second interpolation comparator having a second interpolation input and a third interpolation input, the second interpolation input coupled to the interpolation output and the third interpolation input coupled to the dummy output.

An apparatus includes a comparator. The comparator includes first and second pregain stages, and a switch network coupled to the first and second pregain stages. A plurality of switches in the switch network are operable to provide a feedback path around at least one of the first and second pregain stages. The comparator further includes a latch coupled to the second pregain stage.

An arithmetic circuit includes an auto-zero amplification circuit that compensates an offset of an entered differential signal, and a comparator circuit that converts an output signal from the auto-zero amplification circuit to a digital signal. The auto-zero amplification circuit and comparator circuit are provided in the same package.

A tracking ADC with adaptive slew rate boosting can dynamically adjust one or more of its operational parameters in response to detecting a slew rate limit condition. In some embodiments, slew rate boosting can include increasing the value of a digital error signal in response to detection of a slew rate limit condition. In other embodiments, slew rate boosting can include increasing a clock frequency of the tracking ADC in response to detection of a slew rate limit condition.

Implementations for heat structure for thermal mitigation are described. The described heat structures, for instance, provide a multi-layered structure that optimizes heat spreading and dissipation, as well as wireless performance of wireless devices. A heat structure, for instance, is installed internally in a wireless device adjacent various internal components to absorb heat generated by the components, and to dissipate the heat. According to various implementations, a heat structure is implemented as a thermally conductive layer surrounded by layers of electrically conductive material. Electrically conductive vias can be formed that traverse the thermally conductive layer and form an electrical connection between different electrically conductive layers to mitigate current flow in the thermally conductive layer.

An electronic device which may include an analog-to-digital converter circuit that converts a level of an input signal to digital input values in response to a clock signal, an oscillator that generates the clock signal, a first equalization circuit that generates digital output signals by equalizing the digital input values, a first phase detector circuit that detects phases of the digital output signals and generates digital phase values, a loop filter that generates a first digital output value based on the digital phase values, a second equalization circuit that generates digital intermediate values by equalizing the digital input values, and a second phase detector circuit that detects phases of the digital intermediate values and to generate a second digital output value. The oscillator may adjust a frequency of the clock signal based on the first digital output value and the second digital output value.

An electronic device which may include an analog-to-digital converter circuit that converts a level of an input signal to digital input values in response to a clock signal, an oscillator that generates the clock signal, a first equalization circuit that generates digital output signals by equalizing the digital input values, a first phase detector circuit that detects phases of the digital output signals and generates digital phase values, a loop filter that generates a first digital output value based on the digital phase values, a second equalization circuit that generates digital intermediate values by equalizing the digital input values, and a second phase detector circuit that detects phases of the digital intermediate values and to generate a second digital output value. The oscillator may adjust a frequency of the clock signal based on the first digital output value and the second digital output value.