A system for determining an amplitude of a sinusoidal output waveform from a sensor includes a controller configured to provide a sample signal having a sample frequency that is four times a frequency of a sinusoidal excitation waveform provided to the sensor. The sensor has inductively-coupled primary and secondary windings that produce the sinusoidal output waveform from the secondary winding when the excitation waveform is provided to the primary winding. An analog-to-digital converter measures a first and second voltage of the sensor waveform separated in time by the period of the sample frequency, and the system calculates the amplitude based on the measurements of the first and second voltages.

A light sensor circuit, which comprising a photodiode and a voltage follower. By setting the voltage follower to reduce the influence from the junction capacitance of the photodiode, a required time of a repeat integration module will not be influenced by the photodiode to efficiently keep the performance and the accuracy of the analog to digital converting device when the light sensor circuit is used to the analog to digital converting device in repeat operation.

A control system includes an encoder and a control device that controls a target object. The encoder includes a position information generating unit that generates position information made of a predetermined amount of data and including absolute position data of an object to be detected; a configuration information generating unit that generates configuration information representing a ratio of the absolute position data in the amount of data during serial communication; and a transmission unit that transmits, to the control device, the position information and the configuration information as serial data. The control device includes a reception unit that receives the position information and the configuration information transmitted from the encoder; a storage unit that stores the received configuration information; and a notification unit that performs notification of a configuration mismatch when the stored configuration information does not match the next received configuration information.

A charge sharing circuit includes a charge source having an accumulated first charge and a charge load having an accumulated second charge, where during a charge sharing interval the second charge is less than the first charge. A charge sharing regulator selectively couples between the charge source and the charge load along a charge sharing path. The charge sharing regulator regulates transfer of a shared amount of charge from the charge source to the charge load during the charge sharing interval.

An analog to digital converter (ADC) comprising: a delay circuit having a complementary signal output; a first comparator having an input coupled to the complementary signal output of the delay circuit, the first comparator having a first output and a second output; a first dummy comparator having a first dummy input coupled to the first output and a second dummy input coupled to the second output, the first dummy comparator having a dummy output; a first interpolation comparator having an interpolation output and a first interpolation input coupled to the first output; a second dummy comparator having an input coupled to the interpolation output; and a second interpolation comparator having a second interpolation input and a third interpolation input, the second interpolation input coupled to the interpolation output and the third interpolation input coupled to the dummy output.

A charge sharing circuit includes a charge source having an accumulated first charge and a charge load having an accumulated second charge, where during a charge sharing interval the second charge is less than the first charge. A charge sharing regulator selectively couples between the charge source and the charge load along a charge sharing path. The charge sharing regulator regulates transfer of a shared amount of charge from the charge source to the charge load during the charge sharing interval.

A resolver signal processing apparatus processes a resolver signal output from a resolver by applying an excitation signal generated by an excitation signal generating unit. In particular, the resolver signal processing apparatus includes: a resolver signal processing unit, in which the resolver signal processing unit includes a resolver signal acquiring unit receiving the resolver signal and extracting pole information of the resolver signal, a resolver phase compensating unit compensating a pole acquisition time of extracting the pole information of the resolver signal acquiring unit, and a resolver-digital converter outputting a digital signal by using the pole information extracted from the resolver signal acquiring unit, and a resolver signal processing method using the same.

A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.

A system and method for fast converging gain calibration for phase lock loops (PLL) are herein disclosed. According to one embodiment, a method includes receiving, with a voltage generation circuit, an input value representing a difference between a sampled voltage and a reference voltage, and adjusting, with the voltage generation circuit, the reference voltage by generating a voltage output based on the difference represented by the input value.

A method of operation in an analog-to-digital converter (ADC) includes performing a calibration operation. The calibration operation includes sampling an input analog reference voltage. A sequence of charge sharing transfers is then performed with a charge sharing regulator to transfer an actual amount of charge between a charge source and a charge load based on the input analog reference voltage. The transferred actual amount of charge is compared to a reference charge value corresponding to the reference voltage. A control input to the charge sharing regulator is adjusted to correspondingly adjust charge sharing of a subsequent amount of charge based on the comparing.