The present disclosure provides devices, systems, and methods for time correction. The device may include a first time measurement component configured to measure a receiving time of a valid signal; a correction component configured to collect correction information for correcting the receiving time of the valid signal; and a processing device configured to determine a corrected receiving time of the valid signal by correcting the receiving time of the valid signal based on the correction information.

A single-ended analog signal receiver apparatus is provided, which can cope with an external ground current and an undefined impedance through an AC bootstrap input impedance, while considering electromagnetic compatibility, convert a received single-ended analog signal into a balanced output differential signal, and may provide at a post-stage circuit output an output signal with lower noise through common mode rejection.

A power supply circuit module for a TDC (Time to Digital Converter) includes a first input for receiving a control signal, a second input for receiving a power supply voltage, and an output configured to be connected to the power supply input of the TDC. An active main power supply device is configured to receive the control signal at the input and to contribute on the value of the power supply voltage resulting at an output by a voltage value lower than a first predefined percentage with respect to the nominal power supply voltage. A number N of active secondary power supply devices each are configured to contribute on the value of the power supply voltage resulting at the output by a percentage different from the remaining active secondary power supply devices.

Various embodiments of the present technology may comprise methods and apparatus for a multi-cycle time-based ADC configured to convert an analog signal to a digital value. Methods and apparatus a multi-cycle time-based ADC according to various aspects of the present invention may comprise a plurality of VTCs configured to perform multiple voltage-to-time conversions out-of-phase from each other. The integration times for each VTC may be summed to provide a total integration time, which may then be converted to the digital value.

Various embodiments of the present technology may comprise methods and apparatus for a multi-cycle time-based ADC configured to convert an analog signal to a digital value. Methods and apparatus a multi-cycle time-based ADC according to various aspects of the present invention may comprise a plurality of VTCs configured to perform multiple voltage-to-time conversions out-of-phase from each other. The integration times for each VTC may be summed to provide a total integration time, which may then be converted to the digital value.

A differential voltage-to-time converter (VTC) architecture and method of providing VTC signals are disclosed. The VTC includes a ramp generator that generates a ramp voltage, capacitors having a bottom plate coupled with the ramp generator to receive the ramp voltage, and inverters having inputs coupled to top plates of the capacitors to provide signals based on a sampled signal. A threshold voltage or supply voltage of the inverters tracks a minimum input signal voltage.

A method, apparatus, and energy metering system obtains mains samples of a mains power line signal, performs non-white noise (NWN) filtering of the mains power line signal, obtains adjustable clock source samples of an adjustable clock signal of an adjustable clock oscillator, determines a difference based on the mains samples and the adjustable clock source samples, adjusts an adjustable clock source frequency of the adjustable clock oscillator based on the difference, and applies the adjustable clock source frequency to an analog to digital converter (ADC) to determine a conversion rate of the ADC.

The present invention discloses an analog-to-digital conversion circuit having remained time measuring mechanism is provided. A digital-to-analog conversion (DAC) circuit samples input voltages to generate output voltages. A comparator compares the output voltages to generate a comparison result. A control circuit switches a configuration of the DAC circuit by using a digital code according to the comparison result. A comparison determining circuit sets a stage indication signal at a finished state after the comparison result is generated. A comparison stage counting circuit accumulates a termination number according to the stage indication signal to set a conversion indication signal at the finished state when the termination number reaches a predetermined number. A time accumulating circuit starts to accumulate a remained time when the conversion indication signal is at the finished state and finishes accumulation when a sampling indication signal is at a sampling state.

A sort-and-delay time-to-digital converter (TDC) is provided, made up of a plurality of serially connected sort-and-delay circuits. Each sort-and-delay circuit accepts a time-differential input signal with a first edge separated from a second edge by an input duration of time. The first and second edges are selectively routed as a time-differential output signal with a delayed edge separated from a trailing edge by an output duration of time representing a compression of the input duration of time. Each sort-and-delay circuit also supplies a TDC coded bit (e.g., Gray code) indicating the order in which the first and second edges are routed as leading and trailing edges. The TDC outputs a digital output signal representing the initial input duration of time associated with the initial time-differential input signal received by the initial sort-and-delay circuit. Associated TDC, sort-and-delay, and time amplification methods are also provided.

An LDO regulator includes a voltage-to-time converter configured to convert a fluctuation in an output voltage sensed from an output node into a time domain signal having a pulse type, and output the time domain signal, based on a clock signal; a time-to-voltage converter configured to receive the time domain signal, convert the time domain signal into a first voltage control signal performing first compensation for the output voltage, and output the first voltage control signal; an analog amplifier configured to output a second voltage control signal continuously performing second compensation for the output voltage, regardless of the clock signal; and a first pass transistor configured to drive the output voltage based on the second voltage control signal. The LDO regulator is configured to reduce the fluctuation in the output voltage, based on the first compensation and the second compensation.