An analog counter circuit for use with a digital pixel includes: an input; an output; a first stage electrically coupled to the input that is charged to an initial charge voltage; a second stage that includes an accumulating charge storage device; and a charge transfer device between the first and second stages that includes a transfer voltage. The charge transfer device allows charge from the first stage to pass to the second stage and be accumulated on the accumulating charge storage device as long as a voltage at a node in the first stage is greater than the transfer voltage.

Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.

Digital focal plane arrays (DFPAs) with multiple counters per unit cell can be used to convert analog signals to digital data and to filter the digital data. Exemplary DFPAs include two-dimensional arrays of unit cells, where each unit cell is coupled to a corresponding photodetector in a photodetector array. Each unit cell converts photocurrent from its photodetector to a digital pulse train that is coupled to multiple counters in the unit cell. Each counter in each unit cell can be independently controlled to filter the pulse train by counting up or down and/or by transferring data as desired. For example, a unit cell may perform in-phase/quadrature filtering of homodyne- or heterodyne-detected photocurrent with two counters: a first counter toggled between increment and decrement modes with an in-phase signal and a second counter toggled between increment and decrement modes with a quadrature signal.

An analog to digital converter is provided. The analog to digital converter includes: an arithmetic operator combining an analog input signal with a feedback signal; a loop filter filtering an output signal of the arithmetic operator; a quantizer quantizing an output signal of the loop filter to output a digital signal; and a feedback converting the digital signal to output a feedback signal, in which the quantizer includes: a plurality of VCOs each receiving a positive output signal and a negative output signal of the loop filter and outputting VCO signals; a plurality of samplers receiving the VCO signals output from the plurality of VCOs, respectively and outputting sampled signals; and a phase detector detecting a phase difference in the sampled signals output from the plurality of samplers, respectively, to detect a phase difference in two VCO signals output from the plurality of VCOs, respectively.

A method for non-linearity correction includes receiving a first output signal from a data signal path containing a first analog-to-digital converter and receiving a second output signal from a second analog-to-digital converter. The method also includes generating first non-linearity coefficients using the first output signal and generating second non-linearity coefficients using the first and second output signals. The method further includes applying, by a non-linearity corrector in the data signal path, the first and second non-linearity coefficients to compensate for non-linearity components in a digitized signal output from the first analog-to-digital converter to generate a corrected digitized signal.

An oscillator-based sensor interface circuit includes first and second input nodes arranged to receive first and second electrical signals representative of an electrical quantity, respectively; an analog filter; a first oscillator arranged to receive a first oscillator input signal and a second oscillator different from the first oscillator and arranged to receive a second oscillator input signal; a comparator arranged to compare signals coming from the first and second oscillators; a first feedback element arranged to receive a representation of the digital comparator output signal and to convert the representation into a first feedback signal to be applied to the oscillation means; a digital filter arranged to yield an output signal, being an filtered version of the digital comparator output signal; a second feedback element arranged to receive the output signal and to convert the output signal into a second feedback signal.

In described examples, a circuit includes an integrator. The integrator generates a first signal responsive to an input signal. A trigger circuit is coupled to the integrator and receives the first signal. A charge dump circuit is coupled to the integrator and the trigger circuit. The trigger circuit modifies configuration of the charge dump circuit and the integrator when the first signal is greater than a first threshold.

In described examples, a circuit includes an integrator. The integrator generates a first signal responsive to an input signal. A trigger circuit is coupled to the integrator and receives the first signal. A charge dump circuit is coupled to the integrator and the trigger circuit. The trigger circuit modifies configuration of the charge dump circuit and the integrator when the first signal is greater than a first threshold.

A multi-band remote unit is disclosed. The multi-band remote unit includes a number of radio frequency (RF) front-end circuits configured to generate a number of downlink RF communications signals associated with a number of frequency bands based on a number of downlink digital communications signals, respectively. The multi-band remote unit also includes a digital interface circuit and a digital processing circuit. The digital interface circuit is configured to receive an encapsulated downlink digital communications signal and generate the downlink digital communications signals associated with the frequency bands based on the encapsulated downlink digital communications signal. The digital processing circuit is configured to digitally process the downlink digital communications signals before providing the downlink digital communications signals to the RF front-end circuits. As such, it may be possible to share the digital processing circuit among RF front-end circuits, thus helping to reduce cost and/or power consumption of the multi-band remote unit.

A multi-band remote unit is disclosed. The multi-band remote unit includes a number of radio frequency (RF) front-end circuits configured to generate a number of downlink RF communications signals associated with a number of frequency bands based on a number of downlink digital communications signals, respectively. The multi-band remote unit also includes a digital interface circuit and a digital processing circuit. The digital interface circuit is configured to receive an encapsulated downlink digital communications signal and generate the downlink digital communications signals associated with the frequency bands based on the encapsulated downlink digital communications signal. The digital processing circuit is configured to digitally process the downlink digital communications signals before providing the downlink digital communications signals to the RF front-end circuits. As such, it may be possible to share the digital processing circuit among RF front-end circuits, thus helping to reduce cost and/or power consumption of the multi-band remote unit.