VCO ADCs consume relatively little power and require less area than other ADC architectures. However, when a VCO ADC is implemented by itself, the VCO ADC can have limited bandwidth and performance. To address these issues, the VCO ADC is implemented as a back end stage in a VCO-based continuous-time (CT) pipelined ADC, where the VCO-based CT pipelined ADC has a CT residue generation front end. Optionally, the VCO ADC back end has phase interpolation to improve its bandwidth. The pipelined architecture dramatically improves the performance of the VCO ADC back end, and the overall VCO-based CT pipelined ADC is simpler than a traditional continuous-time pipelined ADC.

Disclosed are a continuous-time delta-sigma analog-to-digital converter and an operation method thereof. More particularly, a continuous-time delta-sigma analog-to-digital converter, including: a linear integrator configured to generate a first output signal corresponding to a preset input voltage based on an operation of a linear Gm circuit that receives the preset input voltage; and a quantizer configured to generate a second output signal corresponding to the first output signal based on an operation of a body-driven VCO that receives the first output signal and to generate a digital output code corresponding to the second output signal based on an operation of a Frequency to Digital Converter (FDC) that receives the second output signal is disclosed.

A method is provided for improving the EMC robustness of Integrated Capacitive Sensor systems with a sensor Signal-Conditioner (SSC). The SSC is connected with a capacitive integrating converter to convert a received signal into a bit stream. An oscillator provides a plurality of sampling frequencies. A counter connected with the capacitive integrating converter collects the bit stream and calculates the digital representative of the physical input which is than stored in an output register. The method includes performing some conversions with different sampling frequencies from the oscillator or a frequency divider by the capacitive integrating Signal-Converter; storing the results of the samplings and using the results in the following cycle to calculate for each sampling frequency a difference to the prior sampling of the same frequency; and calculating the digital representative of the input signal from the external sensing capacitor as the reverse weighted average of the samplings of the different frequencies.

A method is provided for improving the EMC robustness of Integrated Capacitive Sensor systems with a sensor Signal-Conditioner (SSC). The SSC is connected with a capacitive integrating converter to convert a received signal into a bit stream. An oscillator provides a plurality of sampling frequencies. A counter connected with the capacitive integrating converter collects the bit stream and calculates the digital representative of the physical input which is than stored in an output register. The method includes performing some conversions with different sampling frequencies from the oscillator or a frequency divider by the capacitive integrating Signal-Converter; storing the results of the samplings and using the results in the following cycle to calculate for each sampling frequency a difference to the prior sampling of the same frequency; and calculating the digital representative of the input signal from the external sensing capacitor as the reverse weighted average of the samplings of the different frequencies.

In one aspect, an analog-to-digital converter circuit includes a transimpedance amplifier including a feedback capacitor electrically connected between an inverting or a non-inverting input of the transimpedance amplifier and an output of the transimpedance amplifier. The circuit includes an hourglass switch electrically connected on a first side to a first input and a second input, and electrically connected on a second side to the non-inverting input and the inverting input. A fine input current to the transimpedance amplifier is received at the first and second inputs. In a first mode, the hourglass switch electrically connects the first input to the non-inverting input and the second input to the inverting input, and in a second mode, the hourglass switch electrically connects the second input to the non-inverting input and the first input to the inverting input.

A controlled oscillator Analog-to-Digital Converter (ADC) includes an analog interface configured for receiving an analog differential input signal, and configured for providing a differential control signal; first and second controlled oscillators configured for receiving the differential control signal; and a frequency-to-digital converter having a first input coupled to an output of the first controlled oscillator, a second input coupled to an output of the second controlled oscillator, and an output for providing a digital output signal proportional to the analog differential input signal, wherein the analog interface or at least one of the first and second controlled oscillators is configured for receiving at least one disturb signal to prevent locking between the first and second controlled oscillators.

A noise-shaping enhanced (NSE) gated ring oscillator (GRO)-based ADC includes a delay which delays and feedbacks an error signal to an input of the NSE GRO-based ADC. The feedback error signal provides an order of noise-shaping and the error signal is generated at the input of the NSE GRO-based ADC from an input signal, the feedback error signal, and a front-end output. A voltage-to-time converter converts the error signal to the time domain. A GRO outputs phase signals from the time domain error signal by oscillating when the error signal is high and inhibiting oscillation otherwise. A quantization device quantizes the phase signals to generate the front-end output. A quantization extraction device determines a quantization error from the quantized phase signals. A time-to-digital converter digitizes the quantization error to generate a back-end output. An output device generates a second order noise-shaped output based on the front-end and the back-end outputs.

A system and method for suppressing aperture noise resulting from clock jitter associated with a Nyquist analog-to-digital converter (ADC) using self-referred time measurements are provided. The system comprises of a clock, a delay element, a time subtractor, a time-to-digital converter, a filter element, a first digital subtractor, an integrator, a differentiator, and a multiplier. Each of the delay element, time subtractor, time-to-digital converter, filter element, first digital subtractor, integrator, and multiplier is electrically connected in parallel with the ADC, which allows the clock to generate a clock signal that advances into the system and the ADC in order to isolate and suppress the noise aperture associated with the ADC. As such, the architecture of the system is configured to isolate and suppress aperture noise resulting from clock jitter associated with an analog-to-digital converter (ADC) to allow the output signal of the system be independent of the aperture noise.

A voltage-controlled oscillator analog-to-digital converter (VCO-ADC) includes a first source follower coupled between a first input terminal and a first internal node; a first VCO having an input coupled to a second internal node; a first variable resistor coupled between the first internal node and the second internal node; and a digital signal processing component coupled between an output of the first VCO and a output terminal.

A voltage-controlled oscillator analog-to-digital converter (VCO-ADC) includes a first source follower coupled between a first input terminal and a first internal node; a first VCO having an input coupled to a second internal node; a first variable resistor coupled between the first internal node and the second internal node; and a digital signal processing component coupled between an output of the first VCO and a output terminal.