A semi-digital finite impulse response, FIR, filter is configured as a sparse FIR filter and as a minimum phase lag FIR filter. The FIR filter has a delay line composed of a number of sets of delay units sequentially coupled to each other, and where some of the sets of delay units have one or more untapped delay units as part of a cascade of two or more single-sample delay units. An analog summing node is coupled to the taps and produces at its output an analog version of a digital input signal that is fed to an input of the delay line. Other embodiments are also described and claimed.

A phase interpolator with a DAC outputting a first and second value responsive to a control code. A first current mirror generates a first current proportional to the first value. A second current mirror generates a second current proportional to the second value. A first FET pair comprising a first and second FET such that the source terminals of the first FET and the second FET are electrically connected and connect to the first current mirror. A second FET pair comprising a third and fourth FET such that the source terminals of the third FET and the fourth FET are electrically connected and connect to the second current mirror. A first terminal outputs a phase adjusted clock signal as compared to the clock signal, from the first FET and the third FET. A second terminal outputs an inverted phase adjusted clock signal, from the second FET and the fourth FET.

Methods and apparatus for dynamically controlling a quantum computer are described wherein the method includes selecting a first and second digital pulse signal stored in a memory, the first digital pulse signal having a first pulse shape and a first sample rate and the second digital pulse signal having a second pulse shape and a second sample rate, at least the first or the second sample rate being lower than an output sampling rate of a digital-to-analog converter (DAC); forming a digital pulse sequence signal, the forming including applying a first interpolation algorithm to determine a first upsampled digital pulse signal based on the first digital signal and a second interpolation algorithm to determine a second upsampled digital pulse signal based on the second digital signal, the sample rates of the first and second upsampled digital signals matching the sample rate of the DAC; and, providing the digital pulse sequence signal comprising the first and second upsampled digital pulse signals to an input of the DAC to transform the first and second upsampled digital signals into an analog pulse sequence signal for controlling the quantum device.

Provided are, among other things, systems, apparatuses, methods and techniques for converting a discrete-time quantized signal into a continuous-time, continuously variable signal. An exemplary converter preferably includes: (1) multiple oversampling converters, each processing a different frequency band, operated in parallel; (2) multirate (i.e., polyphase) delta-sigma modulators (preferably second-order or higher); (3) multi-bit quantizers; (4) multi-bit-to-variable-level signal converters, such as resistor ladder networks or current source networks; (5) adaptive nonlinear, bit-mapping to compensate for mismatches in the multi-bit-to-variable-level signal converters (e.g., by mimicking such mismatches and then shifting the resulting noise to a frequently range where it will be filtered out by a corresponding bandpass (reconstruction) filter); (6) multi-band (e.g., programmable noise-transfer-function response) bandpass delta-sigma modulators; and/or (7) a digital pre-distortion linearizer (DPL) for canceling noise and distortion introduced by an analog signal bandpass (reconstruction) filter bank.

A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.

An oscillator architecture with pulse-edge tuning. The oscillator includes a signal generator generating at least two signal frequencies, and a logic circuit (such as an AND gate) that combines the signal frequencies to generate a corresponding oscillator signal. The logic circuit includes a pull-up PMOS transistor coupled to a high rail, and a pull-down NMOS transistor coupled to a low rail. Duty cycle tuning/correction circuitry includes high and low side tuning FETs: a high-side tuning PMOS transistor is coupled between the high rail and a source terminal of the pull-up PMOS transistor, and a low-side tuning NMOS transistor is coupled between the low rail and a source terminal of the pull-down NMOS transistor. Both tuning FETs are controlled for operation as a variable resistor by respective high-side and low-side DACs (digital to analog converters) configure to provide a tuning control signals to the tuning FETs (variable resistance) based on respective input digital tuning/correction signals. In an example application, the oscillator design is adapted for a direct conversion RF transmit chain including an I-Path and a Q-Path: the signal generator generates I and Q differential signal frequencies, and each signal frequency is generated by a separate logic circuit (such as an AND gate), including pulse-edge tuning/correction circuitry.

A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.

Provided are, among other things, systems, apparatuses methods and techniques for providing a complete output signal from a set of partial signals, which in turn have been generated by parallel processing paths in the time-interleaved and/or frequency-interleaved conversion of discrete signals to linear signals (i.e., discrete-to-linear conversion). One such apparatus includes a distributed network comprising a plurality of ladder networks through which input signals propagate before being combined to form an output signal.

A D/A converter includes a decoder, a voltage selection circuit, and a voltage selection circuit. The voltage selection circuit includes a plurality of stages of selector blocks in which output of a selector of the selector block at the previous stage is input to a selector of the selector block at the subsequent stage. A plurality of voltages are input to the selector block at the first stage, and the selector block at the final stage outputs a D/A-converted voltage. Each of the plurality of stages of selector blocks includes a plurality of transistors and, of the plurality of transistors forming the selector block, a second transistor on a far side from a power source node is set to a lower threshold voltage than that of a first transistor on a near side from the power source node.

A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.