High performance digital to analog converter

Abstract

A digital-to-analog converter (DAC) may include a conversion block providing a first analog value. The DAC may also include an amplification block for receiving the first analog value and providing a second analog value amplified by an amplification factor. The amplification block may include a first input terminal for receiving the first analog value, a second input terminal, and an output terminal for providing the second analog value. The amplification block may also include a first capacitive element and a second capacitive element. The first and second capacitive elements may determine the amplification factor. The amplification block may further include a control unit for recovering a charge at a first terminal of the second capacitive element, and based thereon, the second analog value.

Claims

1. A memory device comprising: a plurality of memory cells; and a digital-to-analog converter cooperating with said plurality of memory cells and comprising a conversion block configured to receive a digital value and provide a corresponding first analog value, an amplification block configured to receive the first analog value and provide a second analog value amplified by an amplification factor with respect to the first analog value, said amplification block comprising a first input terminal configured to receive the first analog value, a second input terminal, and an output terminal configured to provide the second analog value, said amplification block further comprising a first capacitive element having first and second terminals coupled to the output terminal and the second input terminal, respectively, and a second capacitive element having first and second terminals coupled to the second terminal of the first capacitive element and to a reference terminal, respectively, said first and second capacitive elements determining the amplification factor, and recovery circuitry configured to recover, at each of a plurality of time periods, an operative charge at the first terminal of said second capacitive element, and, based upon the operative charge, the second analog value to the output terminal of said amplification block.

2. The memory device according to claim 1, wherein the plurality of memory cells comprises a plurality of flash memory cells.

3. The memory device according to claim 1, wherein said recovery circuitry comprises: a further first capacitive element having first and second terminals; and a further second capacitive element having a first terminal coupled to the second terminal of the further first capacitive element, and a second terminal coupled to the reference terminal.

4. The memory device according to claim 3, wherein said recovery circuitry comprises: a first switching element, in a first or second configuration of the first switching element, the first terminal of the further second capacitive element being respectively coupled to or uncoupled from the first terminal of the second capacitive element; and a second switching element, in a first or second configuration of the second switching element, the first terminal of the further first capacitive element being respectively coupled to or uncoupled from the output terminal of said amplification block.

5. The memory device according to claim 4, wherein said recovery circuitry is configured to: switch the first switching element and the second switching element in the second configuration; charge, with the first and second switching elements in the second configuration, the first terminal of the further first capacitive element to a recovery charge; and switch the first switching element and the second switching element in the first configuration, in response to the switching, the recovery charge at the first terminal of the further second capacitive element and the charge at the first terminal of the second capacitive element being equalized to the operative charge.

6. The memory device according to claim 5, wherein said recovery circuitry further comprises: a third switching element, in a first or second configuration of the third switching element, the first terminal of the further first capacitive element being respectively coupled to or uncoupled from the reference terminal; and a fourth switching element, in a first or second configuration of the fourth switching element, the first terminal of the further second capacitive element being respectively coupled to or uncoupled from the reference terminal.

7. The memory device according to claim 6, wherein said recovery circuitry is configured to: switch the first and second switching elements in the second configuration and the third and fourth switching elements in the first configuration, in response to the switching, the first terminal of the further second capacitive element being charged to a reference charge; and switch the first, third, and fourth switching elements in the second configuration and the second switching element in the first configuration, in response to the switching, the first terminal of the further second capacitive element being charged to the recovery charge from the reference charge.

8. The memory device according to claim 3, wherein said first capacitive element has a first capacitive value and said second capacitive element has a second capacitive value, and wherein said further first capacitive element has a further first capacitive value equal to the first capacitive value and said further second capacitive element has a further second capacitive value equal to the second capacitive value.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram of a flash memory device according to an embodiment of the invention.

(2) FIG. 2 is a schematic diagram of a DAC of the flash memory device according to an embodiment of the invention.

(3) FIG. 3 is a graph of qualitative time diagrams of control signals and of an input voltage of an amplification block of the DAC according to an embodiment of the invention.

DETAILED DESCRIPTION

(4) The approach according to one or more embodiments, as well as further features and the related advantages, will be best understood with reference to the following detailed description, given purely by way of non limitative example only, to be read in conjunction with the accompanying figures (wherein corresponding elements are indicated by same or similar references and their explanation is not repeated for the sake of brevity).

(5) With particular reference to FIG. 1, a flash memory device 100 (for example, a NOR flash memory device) according to an embodiment is illustrated. The flash memory device 100, integrated in a chip of semiconductor material, comprises a matrix 105 of electrically erasable and programmable memory cells 110.

(6) Each memory cell 110 typically comprises a floating gate MOS transistor (only one shown in the figure, and illustrated by a typical circuit representation thereof), which has a bulk terminal B, a drain terminal D, a source terminal S, a gate terminal G, and a floating gate region electrically insulated. Each memory cell 110 is adapted to store a corresponding information bit, represented by a threshold voltage of the corresponding floating gate MOS transistor (in turn depending on the amount of electric charges trapped in the floating gate).

(7) The flash memory device 100 comprises peripheral components (for example, decoders, multiplexers, buffers, sense amplifiers, converters, control unit) configured to access selected memory cells 110 and perform operations on the same (for example, programming, erasing, reading, soft-programming, programming verify, erasing verify, reading verify and soft-programming verify). To execute each one of these operations (or memory operations), the terminals of the floating gate MOS transistor of the memory cell 110 (and, particularly, the gate G and/or bulk B terminals) are biased (for the all time length T.sub.OP of the selected memory operation) to respective bias voltages V.sub.P.

(8) For example, during the erasing, programming, programming verify, erasing verify, reading verify, and soft-programming verify operations, the bias voltage V.sub.P applied to the gate terminals G of the selected memory cells 110 is equal to 10V, 9V, 6.3V, 4.4V, 5.3V and 2.8V, respectively, whereas during the erasing/soft-programming operation, the bias voltage V.sub.P applied to the bulk B/gate G terminals comprises (voltage) pulses having progressively increasing values (for example, from 4V to 10.75V with a 0.3V step, and from 2.5V to 7V with a 0.125V step, respectively).

(9) In the following, for the sake of exposition brevity, only components and aspects of the flash memory device 100 relevant to the understanding of the invention (i.e., relating to the terminals biasing) will be introduced and described.

(10) The flash memory device 100 comprises a digital-to-analog converter (hereinafter, DAC) 115 for generating the bias voltage V.sub.P from a corresponding digital value D.sub.D and biasing the selected memory cells 110 (as conceptually represented in the figure by the generic arrow connection between the DAC and the matrix 105), and a control unit 120 for providing the digital value D.sub.D to the DAC 115 according to the memory operation to be performed (and, hence, according to the required corresponding bias voltage V.sub.P). Preferably, as illustrated, the control unit 120 also provides one or more (e.g., three) control signals 1,2,3 to the DAC 115. As will be better discussed in the following, these control signals 1,2,3 allow a recovery of electric charge in the DAC 115.

(11) With reference now to FIG. 2, the DAC 115 according to an embodiment is schematically illustrated.

(12) The DAC 115 comprises a conversion block 205 (e.g., a R-2R resistor ladder network) for receiving the digital value D.sub.D and providing a corresponding (voltage or current) analog value D.sub.A, and an amplification block 210 for amplifying (by a suitable amplifying factor, or gain G) such analog value D.sub.A thereby obtaining said bias voltage V.sub.P.

(13) The amplification block 210 comprises, in the illustrated embodiment, an operational amplifier 210.sub.OA. The operational amplifier 210.sub.OA (illustrated in FIG. 2 by its conventional circuit symbol) is not limiting for the embodiments, as it may be implemented according to specific design requirements (for example, architecture of the conversion block 205, and/or electrical quantity, voltage or current, used to provide the analog value D.sub.A). For example, in the embodiment herein considered, wherein the conversion block 205 has a R-2R resistor ladder architecture (so that the analog value D.sub.A is provided in the form of a current), the operational amplifier 210.sub.OA may be implemented by a transconductance input stage and an amplifying output stage arranged in cascade (not shown). The operational amplifier 210.sub.OA comprises a non-inverting input terminal (denoted by the sign + in the figure) for receiving the analog value D.sub.A from the conversion block 205, an inverting input terminal (denoted by the sign in the figure), and an output terminal for providing the bias voltage V.sub.P.

(14) In the proposed approach, the amplification block 210 further comprises a capacitive network 210.sub.C connected (or, in part, selectively connected, as discussed below) to the operational amplifier 210.sub.OA. More particularly, such capacitive network 210.sub.C comprises a capacitor (or other capacitive element) C.sub.A whose terminals T.sub.A1 and T.sub.A2 are connected to the output terminal and to the inverting input terminal, respectively, of the operational amplifier 210.sub.OA, and a further capacitor (or other capacitive element) C.sub.B whose terminals T.sub.B1 and T.sub.B2 are connected to the terminal T.sub.A2 of the capacitor C.sub.A (and hence to the inverting input terminal of the operational amplifier 210.sub.OA) and to a reference terminal (preferably, a ground terminal providing a ground voltage, for example 0V), respectively.

(15) In other words, the operational amplifier 210.sub.OA and the capacitors C.sub.A,C.sub.B define a feedback configuration, wherein the gain G of the amplification block 210 depends on the capacitance values of the capacitors C.sub.A,C.sub.B (hereinafter denoted by C.sub.A, C.sub.B, respectively), namely:

(16) $G=\frac{\left(C_A+C_B\right)}{C_A}$

(17) Moreover, the capacitors CA,CB define a capacitive partition network between the output terminal of the operational amplifier 210OA and the ground terminal, so that the voltage at the terminals TA2,TB1 (that, as representing also the voltage at the inverting input terminal of the operational amplifier 210OA, will be referred to as input voltage VAB hereinafter) depends on the bias voltage VP and on the ratio between the capacitance values CA,CB of the capacitors CA,CB, namely:

(18) $V_{\mathrm{AB}}=V_P\frac{C_A}{C_A+C_B}=V_P\frac{1}{G}$

(19) The use of a capacitive network rather than, as in the known approaches, of a resistive network, has several advantages. In particular, for the same gain G, the making of a capacitive network determines, with respect to a resistive network, lower tolerances and lower parasitic capacitive couplings (and therefore fewer limitations in terms of bandwidth), as well as greatly reduced electric power consumption.

(20) Furthermore, for the same gain G, a capacitive network involves area occupation significantly lower than a resistive network. For example, a capacitive network with capacitance values C.sub.A, C.sub.B equal to 150 fF, 3.45 pF, respectively, occupies an area of the order of 1300 m.sup.2, whereas a resistive network would, for the same gain (G23 in the example at issue), would occupy an area of the order of 4000 m.sup.2.

(21) As shown in FIG. 2, the capacitive network 210.sub.C further comprises a (e.g., capacitive) recovery section for periodically recovering (for example, at each recovery period T.sub.R), the charge at the terminal T.sub.A2,T.sub.B1 to an operative value thereof throughout the execution of the memory operation (i.e., for the all the time length T.sub.OP)with such operative value that represents the expected charge value, by virtue of the proposed circuit configuration, when the bias voltage V.sub.P is at an ideal value V.sub.P depending on the memory operation to be performed.

(22) Indeed, due to leakage phenomena that affect the capacitors, the charge at the terminal T.sub.A2,T.sub.B1 decreases over time with respect to its operative value. This affects the bias voltage V.sub.P at the output terminal of the operational amplifier 210.sub.OA (with respect to its ideal value V.sub.P), thus impairing the biasing of the selected memory cells (and, therefore, the operation of the flash memory device 100).

(23) The recovery period T.sub.R, not limiting for the embodiments, may be chosen according to specific design requirements. Preferably, the recovery period T.sub.R is sufficiently lower than the time length T.sub.OP to allow several recovery stages during the execution of a same memory operation.

(24) In the exemplary illustrated embodiment, the recovery capacitive section comprises a recovery capacitor (or other capacitive element) C.sub.AR having a terminal T.sub.AR1 adapted to be selectively connected to the output terminal of the operational amplifier 210.sub.OA or to the reference terminal, and a terminal T.sub.AR2 adapted to be selectively connected to the terminals T.sub.A2,T.sub.B1 (and hence to the inverting input terminal of the operational amplifier 210.sub.OA) or to the reference terminal. The recovery capacitive section further includes a further recovery capacitor (or other capacitive element) C.sub.BR having a terminal T.sub.BR1 connected to the terminal T.sub.AR2 (and therefore also selectively connected to the inverting input terminal of the operational amplifier 210.sub.OA or to the reference terminal), and a terminal T.sub.BR2 connected to the reference terminal.

(25) Advantageously, the capacitance values of the recovery capacitors C.sub.AR, C.sub.BR (hereinafter, denoted by C.sub.AR, C.sub.BR, respectively) are chosen, respectively, equal to the capacitance values C.sub.R, C.sub.B of the capacitors C.sub.A, C.sub.B (i.e., C.sub.A=C.sub.AR and C.sub.B=C.sub.BR), so that the gain G of the amplification block 210 is unchanged even when the capacitive recovery section is connected to the operational amplifier 210.sub.OA. In this condition, in fact, as can be easily verified, with the terminal T.sub.AR1 connected to the output terminal of the operational amplifier 210.sub.OA and the terminals T.sub.AR2,T.sub.BR1 connected to the terminals T.sub.A1,T.sub.B1 the gain G of the amplification block 210 is still equal to:

(26) $G=\frac{\left(C_A+C_B\right)}{C_A}$

(27) Back to FIG. 2, the capacitive network 210C also comprises one or more (e.g., four) switching elements (in the following, switches) SW1, SW2, SW3, SW4 for enabling the selective connection of the terminals TAR1 and TAR2,TBR1.

(28) As visible in the figure, the switch S.sub.W1 enables/disables the connection between the terminals T.sub.AR2, T.sub.BR1 and the terminals T.sub.A2,T.sub.B1 according to the control signal .sub.1 (for example, according to an assertion/de-assertion thereof), the switch S.sub.W2 enables/disables the connection between the terminal T.sub.AR1 and the output terminal of the operational amplifier 210.sub.OA according to the control signal .sub.2 (for example, according to an assertion/de-assertion thereof), and the switches S.sub.W3,S.sub.W4 enable/disable the connection between the terminals T.sub.AR1,T.sub.BR1, respectively, and the reference terminal according to the control signal .sub.3 (for example, according to an assertion/de-assertion thereof).

(29) In the following, for the sake of ease, the effects of charge transfers (to and from the terminal T.sub.A2,T.sub.B1) on the bias voltage V.sub.P will be discussed without taking into account the feedback action (since, as far as the discussed aspects of the invention are concerned, a discussion that takes into account such an action would lead to similar considerations). Therefore, in the following, the charge transfers (to and from the terminal T.sub.A2,T.sub.B1) are considered to affect only the input voltage V.sub.AB, with the bias voltage V.sub.P that instead will be considered constant (and substantially equal to its ideal value V.sub.P).

(30) The operation of the DAC 115 may be summarized as follows (with joint reference to FIG. 3, which shows, according to an embodiment, qualitative time diagrams of the control signals .sub.1,.sub.2,.sub.3 and of the input voltage V.sub.AB in a generic biasing phase).

(31) At the start of the selected memory operation (time instant t.sub.0), and up to a following time instant decreeing the start of the recovery phase (time instant t.sub.1), the control signals .sub.1,.sub.2 are asserted (for example, at a high logic level), and the control signal .sub.3 is de-asserted (for example, at a low logic level). In this condition, at the time instant t.sub.0, the bias voltage V.sub.P is at the ideal value V.sub.P (depending on the ongoing memory operation), and the input voltage V.sub.AB is equal to an ideal value thereof V.sub.AB (also depending on the ongoing memory operation), namely:

(32) ${\underset{\_}{V}}_{\mathrm{AB}}={\underset{\_}{V}}_P\frac{C_A}{\left(C_A+C_B\right)}={\underset{\_}{V}}_P\frac{1}{G}$

(33) Because of the dispersion phenomena (for example, leakage currents IL, not shown) affecting the capacitors CA, CB, and CAR, CBR, between the time instant t0 and the time instant t4 (i.e., the recovery period TR), and neglecting (as previously mentioned) the feedback action, the input voltage VAB decreases over time, and differs with respect to its ideal value VAB.

(34) In particular, between the time instant t.sub.0 and the time instant t.sub.1, the capacitors C.sub.A, C.sub.B and C.sub.AR, C.sub.BR (connected to each other by the switch S.sub.W1), i.e. the terminals T.sub.A2,T.sub.B1 and T.sub.AR2, T.sub.BR1 will experience a loss of electric charge by an amount Q.sub.1[t.sub.1t.sub.0] equal to:

(35) $Q_1\left(t_1-t_0\right)=\frac{I_L\left(t_1-t_0\right)}{2}$

(36) Similarly, between the time instant t0 and the time instant t1, the terminals TA2,TB1 and TAR2,TBR1 (connected to each other by the switch SW1), and hence the input voltage VAB, experience a voltage decrease by an amount VAB[t1t0] equal to:

(37) $V_{\mathrm{AB}}\left[t_1-t_0\right]=\frac{I_L\left(t_1-t_0\right)}{\left(C_A+C_B+C_{\mathrm{AR}}+C_{\mathrm{BR}}\right)}$
or, in the example at issue wherein C.sub.A=C.sub.AR and C.sub.B=C.sub.BR:

(38) $V_{\mathrm{AB}}\left[t_1-t_0\right]=\frac{I_L\left(t_1-t_0\right)}{2\left(C_A+C_B\right)}$

(39) At the time instant t1, the control signal 1 is de-asserted (with the control signal 2 still asserted and the control signal 3 still de-asserted). In this condition, the capacitors CA and CB, in series with each other, and the recovery capacitors CAR and CBR, also in series with each other, are in parallel. As will be clear shortly, the de-assertion of the control signal 1 before the de-assertion of the control signal 2 and of the assertion of the control signal 3 avoids unwanted connections of the terminals TA2,TB1 to the ground terminal (and the subsequent discharging thereof to the ground voltage).

(40) Subsequently, time instant t.sub.2, the control signal .sub.2 is de-asserted and the control signal .sub.3 is asserted (with the control signal .sub.1 still de-asserted). In this condition, the recovery capacitors C.sub.AR, C.sub.BR are insulated (i.e., disconnected) from the capacitors C.sub.A,C.sub.B and from the operational amplifier 210.sub.OA, and the terminals T.sub.AR1 and T.sub.AR2,T.sub.BR1 are charged to a reference charge. In the exemplary considered embodiment, the terminals T.sub.AR1 and T.sub.AR2,T.sub.BR1, connected to the ground terminal, are discharged down to the ground voltage. In this way, the voltage across the recovery capacitors C.sub.AR,C.sub.BR is initialized at the ground voltage.

(41) Such initialization, although not necessary in basic embodiments (wherein the switches S.sub.W3,S.sub.W4 and the control signal .sub.3 may also be omitted), is particularly advantageous since it allows quickly updating the input voltage V.sub.AB to an ideal value V.sub.AB* different from (i.e., higher or lower than) the ideal value V.sub.AB. This may happen, for example, if, during a recovery phase, the bias voltage V.sub.P has to be changed (from the ideal value V.sub.P to a different ideal value V.sub.P*) for performing a different memory operation.

(42) At a time instant t.sub.3, sufficiently following the time instant t.sub.2 to allow the complete initialization of the voltage across the recovery capacitors C.sub.AR,C.sub.BR, the control signal .sub.2 is asserted again and the control signal .sub.3 is de-asserted again (with the control signal .sub.1 still de-asserted).

(43) In this condition, the terminal T.sub.AR1 is connected again to the output terminal of the operational amplifier 210.sub.OA for receiving the bias voltage V.sub.P. In this way, a partition of the bias voltage V.sub.P will be set at the terminals T.sub.AR2,T.sub.BR1as will be easily understood, in the absence of initialization of the voltage across the recovery capacitors C.sub.AR,C.sub.BR the terminals T.sub.AR2,T.sub.BR1 may be charged more slowly to this voltage.

(44) In particular, the voltage at the terminal T.sub.AR2,T.sub.BR1 is equal to:

(45) ${\underset{\_}{V}}_P=\frac{C_{\mathrm{AR}}}{\left(C_{\mathrm{AR}}+C_{\mathrm{BR}}\right)}$
or, in the example at issue wherein C.sub.A=C.sub.AR and C.sub.B=C.sub.BR:

(46) ${\underset{\_}{V}}_P=\frac{C_A}{\left(C_A+C_B\right)}$

(47) This voltage at the terminal TAR2,TBR1 is equivalent to an electric charge that, as will be explained shortly, is used for recovering the operative charge at the terminal TA2,TB1 (hereinafter, recovery charge).

(48) At the same time (i.e., between the time instant t.sub.1 and the time instant t.sub.4), the capacitors C.sub.A,C.sub.B (not connected to the capacitors C.sub.AR, C.sub.BR) i.e. the terminals T.sub.A2,T.sub.B1 and T.sub.AR2,T.sub.BR1, experience a loss of electric charge by an amount Q.sub.2[t.sub.4t.sub.1] equal to:
Q.sub.2[t.sub.4t.sub.1]=I.sub.L(t.sub.4t.sub.1)

(49) Therefore, the total electric charge QT[t4t0] lost between the time instant t0 and the time instant t4 is equal to:

(50) 0$\begin{array}{c}{Q}_T\left[t_4-t_0\right]=Q_1\left[t_1-t_0\right]+Q_2\left[t_4-t_1\right]=\\ =\frac{I_L\left(t_1-t_0\right)}{2}+I_L\left(t_4-t_1\right)=\\ =\frac{I_L\left(T_R-T_R\right)}{2}+I_L{T}_R=\\ =\frac{I_L\left(T_R+T_R\right)}{2}\end{array}$
being T.sub.R=(t.sub.4t.sub.0) the recovery period, and T.sub.R=(t.sub.4t.sub.1).

(51) Similarly, between the time instant t1 and the time instant t4, the input voltage VAB at the terminals TA2,TB1 (which are disconnected from the terminals TAR2,TBR1), experience a voltage decrease by an amount VAB[t4t1] equal to

(52) $V_{\mathrm{AB}}\left[t_4-t_1\right]=\frac{I_L\left(t_4-t_1\right)}{\left(C_A+C_B\right)}$

(53) Therefore, the overall change of the voltage at the terminal TA2,TB1 during a whole recovery period TR=t4t0 is given by:

(54) $\begin{array}{c}{V}_{\mathrm{AB}}\left[t_4-t_0\right]=V_{\mathrm{AB}}\left[t_4-t_1\right]+V_{\mathrm{AB}}\left[t_1-t_0\right]=\\ =\frac{I_L\left(T_R-T_R\right)}{2\left(C_A+C_B\right)}+\frac{I_L\left(T_R\right)}{\left(C_A+C_B\right)}=\\ =\frac{I_L\left(T_R+T_R\right)}{2\left(C_A+C_B\right)}\end{array}$

(55) Finally, time instant t4, the control signal 1 is asserted again (with the control signal 2 still asserted and the control signal 3 still de-asserted). The assertion of the control signal 1 enables the connection between the terminals TA2,TB1 and the terminals TAR2,TBR1, and the equalization of the corresponding electric charges.

(56) Ideally, the DAC 115 may be sized and configured in such a way that this equalization restores the terminal T.sub.A2,T.sub.B1 to the ideal value V.sub.AB (i.e., in terms of electric charge, to the operative charge).

(57) In the practical example herein considered, however, at full performance (i.e., after a number of recovery periods, and hence of equalizations), the input voltage V.sub.AB at the time instant t.sub.0 of a current recovery period takes a value V.sub.ABf lower than the ideal value V.sub.AB and, as can be easily verified, equal to:

(58) ${\underset{\_}{V}}_{\mathrm{ABf}}={\underset{\_}{V}}_P\frac{C_A}{\left(C_A+C_B\right)}-\frac{I_L\left(T_R+T_R\right)}{2\left(C_A+C_B\right)}$
whereas the input voltage V.sub.AB, at the time instant t.sub.4 of the same recovery period, takes a value V.sub.ABf that, by virtue of the electric charge lost due to leakage currents I.sub.L during the recovery period, is lower than the value V.sub.ABf by the above mentioned amount V.sub.AB[t.sub.4t.sub.0], namely:

(59) ${\underset{\_}{V}}_{\mathrm{ABi}}={\underset{\_}{V}}_{\mathrm{ABf}}-V_{\mathrm{AB}}\left[t_4-t_0\right]={\underset{\_}{V}}_{\mathrm{ABi}}={\underset{\_}{V}}_P\frac{C_A}{\left(C_A+C_B\right)}-\frac{I_L\left(T_R+T_R\right)}{2\left(C_A+C_B\right)}-\frac{I_L\left(T_R+T_R\right)}{2\left(C_A+C_B\right)}={\underset{\_}{V}}_{\mathrm{ABi}}={\underset{\_}{V}}_P\frac{C_A}{\left(C_A+C_B\right)}-\frac{I_L\left(T_R+T_R\right)}{\left(C_A+C_B\right)}$

(60) In terms of electric charge, in the practical example herein considered, at full performance, the charge at the terminal TA2,TB1 differs from the operative charge (similarly to that discussed above, in terms of voltage, for the input voltage VAB).

(61) Because of the recovery capacitors C.sub.AR,C.sub.BR, the adjustment of the bias voltage V.sub.P of the DAC 115 is affected by an error E.sub.R given by:

(62) $E_R=G\frac{I_L\left(T_R+T_R\right)}{\left(C_A+C_B\right)}$

(63) According to specific design requirements, this error ER may be arbitrarily reduced (for example, by acting on parameters such as TR, CA and/or CB). The use of the recovery section is advantageous as it may ensure high speed and accuracy of the DAC 115 when generating the bias voltage V.sub.P, while ensuring very low area occupation, costs, and power consumption.

(64) As mentioned above, for the sake of ease, the effects of charge transfers (to and from the terminal T.sub.A2,T.sub.B1) on the bias voltage V.sub.P and on the input voltage V.sub.AB have been discussed by deliberately ignoring the feedback action. Briefly, taking into consideration the feedback action too, the aforesaid charge transfers affect, ideally, only the bias voltage V.sub.P, which is subject to variations (that are unwanted, in the described application) adapted to keep the input voltage V.sub.AB stable.

(65) Anyway, as will be apparent to a person skilled in the art, a discussion that takes into account the feedback action would lead to considerations and results similar to those described above. To satisfy local and specific requirements, a person skilled in the art may apply to the approach described above many logical and/or physical modifications and alterations.

(66) More specifically, although this approach has been described with a certain degree of particularity with reference to one or more embodiments thereof, it should be understood that various omissions, substitutions and changes in the form and details as well as other embodiments are possible. Particularly, different embodiments of the invention may even be practiced without the specific details (such as the numerical examples) set forth in the preceding description to provide a more thorough understanding thereof; conversely, well-known features may have been omitted or simplified in order not to obscure the description with unnecessary particulars. Moreover, it is expressly intended that specific elements and/or method steps described in connection with any embodiment may be incorporated in any other embodiment as a matter of general design choice. In any case, ordinal qualifiers or the like are merely used as labels for distinguishing elements with the same name but do not connote any priority, precedence or order. Moreover, the terms including, comprising, having and containing (and any of their forms) should be understood with an open and non-exhaustive meaning (i.e., not limited to the recited elements), the terms based on, dependent on, according to, function of (and any of their forms) should be understood as a non-exclusive relationship (i.e., with possible further variables involved) and the term a should be understood as one or more elements (unless expressly stated otherwise).