An optical network includes a transmitting portion configured to (i) encode an input digitized sequence of data samples into a quantized sequence of data samples having a first number of digits per sample, (ii) map the quantized sequence of data samples into a compressed sequence of data samples having a second number of digits per sample, the second number being lower than the first number, and (iii) modulate the compressed sequence of data samples and transmit the modulated sequence over a digital optical link. The optical network further includes a receiving portion configured to (i) receive and demodulate the modulated sequence from the digital optical link, (ii) map the demodulated sequence from the second number of digits per sample into a decompressed sequence having the first number of digits per sample, and (iii) decode the decompressed sequence.

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

Systems and methods according to one or more embodiments provide a low power current steering digital-to-analog converter. In one example, a device includes a current cell including a plurality of switches. The device further includes a current cell controller configured to selectively operate the plurality of switches. The plurality of switches is selectively operated to cause the current cell to generate a current signal in response to a first data signal. The plurality of switches is selectively operated to disable the current cell in an absence of the first data signal. The plurality of switches is selectively operated to transition the current cell to a common mode state before the current cell receives the first data signal. Related systems and methods are also provided.

Systems and methods according to one or more embodiments provide a low power current steering digital-to-analog converter. In one example, a device includes a current cell including a plurality of switches. The device further includes a current cell controller configured to selectively operate the plurality of switches. The plurality of switches is selectively operated to cause the current cell to generate a current signal in response to a first data signal. The plurality of switches is selectively operated to disable the current cell in an absence of the first data signal. The plurality of switches is selectively operated to transition the current cell to a common mode state before the current cell receives the first data signal. Related systems and methods are also provided.

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

A digitally-controlled power amplifier (DPA) includes a radio frequency digital-to-analog converter (RF-DAC) constructed from nonlinearly weighted PA segments, a multiphase RF drive signal generator that drives the PA segments, and overdrive voltage control circuitry. The nonlinear weighting of the PA segments intrinsically compensates for amplitude-code-word dependent amplitude distortion (ACW-AM distortion) involved in the operation of the RF-DAC and the multiphase RF drive signal generator facilitates ACW-dependent phase distortion (ACW-PM distortion) reduction, thus obviating the need for complicated and efficiency-degrading digital predistortion. The overdrive voltage control circuitry is used to fine tune the RF output of the DPA and compensate for other non-idealities and external influences such as process, voltage, temperature (PVT), frequency and/or load impedance variations.

Multipliers and Multiply-Accumulate (MAC) circuits are fundamental building blocks in signal processing, including in emerging applications such as machine learning (ML) and artificial intelligence (AI) that predominantly utilize digital-mode multipliers and MACs. Generally, digital multipliers and MACs can operate at high speed with high resolution, and synchronously. As the resolution and speed of digital multipliers and MACs increase, generally the dynamic power consumption and chip size of digital implementations increases substantially that makes them impractical for some ML and AI segments, including in portable, mobile, near edge, or near sensor applications. The multipliers and MACs utilizing the disclosed current mode data-converters are manufacturable in main-stream digital CMOS process, and they can have medium to high resolutions, capable of low power consumptions, having low sensitivity to power supply and temperature variations, as well as operating asynchronously, which makes them suitable for high-volume, low cost, and low power ML and AI applications.

An optical network includes a transmitting portion configured to (i) encode an input digitized sequence of data samples into a quantized sequence of data samples having a first number of digits per sample, (ii) map the quantized sequence of data samples into a compressed sequence of data samples having a second number of digits per sample, the second number being lower than the first number, and (iii) modulate the compressed sequence of data samples and transmit the modulated sequence over a digital optical link. The optical network further includes a receiving portion configured to (i) receive and demodulate the modulated sequence from the digital optical link, (ii) map the demodulated sequence from the second number of digits per sample into a decompressed sequence having the first number of digits per sample, and (iii) decode the decompressed sequence.

A digitally-controlled power amplifier (DPA) includes a radio frequency digital-to-analog converter (RF-DAC) constructed from nonlinearly weighted PA segments, a multiphase RF drive signal generator that drives the PA segments, and overdrive voltage control circuitry. The nonlinear weighting of the PA segments intrinsically compensates for amplitude-code-word dependent amplitude distortion (ACW-AM distortion) involved in the operation of the RF-DAC and the multiphase RF drive signal generator facilitates ACW-dependent phase distortion (ACW-PM distortion) reduction, thus obviating the need for complicated and efficiency-degrading digital predistortion. The overdrive voltage control circuitry is used to fine tune the RF output of the DPA and compensate for other non-idealities and external influences such as process, voltage, temperature (PVT), frequency and/or load impedance variations.

A method for differentiator-based compression of digital data includes (a) using a subtraction module, subtracting a predicted signal from a sample of an original signal to obtain an error signal, (b) using a quantization module, quantizing the error signal to obtain a quantized error signal, and (c) generating the predicted signal using a least means square (LMS)-based filtering method.