An analog-to-digital converter (ADC) includes a loop filter having an input for receiving an analog input signal; a quantizer having an input coupled to an output of the loop filter, and an output for providing a digital output signal; and a digital-to-analog converter (DAC) having an input coupled to an output of the quantizer, and an output coupled to the loop filter, wherein the DAC includes at least one always-on DAC element, and a plurality of on-demand DAC elements.

An electronic device may include a digital to analog converter receiving digital signals and outputting analog signals based on the received digital signals. The electronic device may also include a power source to supply current to the digital to analog converter. The digital to analog converter may include a first resistor ladder section to electrically couple an output node of the digital to analog converter to the power source via a first number of resistors in series. The digital to analog converter may also include a second resistor ladder section to electrically couple the output node to a reference voltage via a second number of resistors in series. The sum of the first number of resistors in series and the second number of resistors in series may be the same for each of the different analog signals.

An electronic control unit includes a pair of D/A conversion circuits, which performs D/A conversion processing of a pair of digital data and outputs a pair of analog signals. Each of the pair of D/A conversion circuits performs the D/A conversion processing by splitting input digital data into more-significant digital data and less-significant digital data. More-significant D/A conversion part performs analog conversion processing in accordance with the more-significant digital data by using an element string circuit, which outputs split voltages by splitting predetermined reference voltages. The more-significant conversion circuits output a maximum value and a minimum value in absolute voltage ranges, which are different from each other, in accordance with the more-significant digital data. Less-significant conversion parts perform analog conversion processing in accordance with less-significant digital data by using the maximum value and the minimum value of the different absolute voltage ranges, which are outputted from the more-significant D/A conversion parts, as reference voltages. The element string circuit is shared by the pair of D/A conversion circuits.

An electronic control unit includes a pair of D/A conversion circuits, which performs D/A conversion processing of a pair of digital data and outputs a pair of analog signals. Each of the pair of D/A conversion circuits performs the D/A conversion processing by splitting input digital data into more-significant digital data and less-significant digital data. More-significant D/A conversion part performs analog conversion processing in accordance with the more-significant digital data by using an element string circuit, which outputs split voltages by splitting predetermined reference voltages. The more-significant conversion circuits output a maximum value and a minimum value in absolute voltage ranges, which are different from each other, in accordance with the more-significant digital data. Less-significant conversion parts perform analog conversion processing in accordance with less-significant digital data by using the maximum value and the minimum value of the different absolute voltage ranges, which are outputted from the more-significant D/A conversion parts, as reference voltages. The element string circuit is shared by the pair of D/A conversion circuits.

A digital to analog converter is provided, including a buffer circuit, a current switch circuit, and a weighted current generating circuit. The buffer circuit receives an N-bit digital signal and a clock signal, accordingly outputs N switch control signals. The current switch circuit includes N switches which are connected or disconnected according the switch control signals. The weighted current generating circuit includes M current source arrays, where each current source array outputs K output currents. Current values of each output current of each current source array respectively ascend in a binary-weighted manner. A minimum output current of an mth current source array is two times of a maximum output current of a (m−1)th current source array, N is obtained by multiplying M by K, and 1≦m≦M. An output of the digital to analog converter is a total current value of the output currents outputted by the M current source arrays.

A digital to analog converter is provided, including a buffer circuit, a current switch circuit, and a weighted current generating circuit. The buffer circuit receives an N-bit digital signal and a clock signal, accordingly outputs N switch control signals. The current switch circuit includes N switches which are connected or disconnected according the switch control signals. The weighted current generating circuit includes M current source arrays, where each current source array outputs K output currents. Current values of each output current of each current source array respectively ascend in a binary-weighted manner. A minimum output current of an mth current source array is two times of a maximum output current of a (m−1)th current source array, N is obtained by multiplying M by K, and 1≦m≦M. An output of the digital to analog converter is a total current value of the output currents outputted by the M current source arrays.

The systems and methods discussed herein utilized a wireless or wired transceiver having a transmitter and a receiver. The transceiver is configured to reduce distortion contributions associated with echo cancelling. The transmitter provides a replica signal and a transmit signal. The replica signal and the transmit signal can be provided using a common switch.

A digital-to-analog conversion circuit, a data driver including the same, and a display device are provided. The circuit includes: a reference voltage generation part, generating a reference voltage group having different voltage values; a decoder, selecting and outputting multiple reference voltages with overlapping from the reference voltage group based on the digital data signal; an amplification circuit, where m (m being an integer of 1 or more and less than x) of first to x.sup.th input terminals respectively receive m of multiple reference voltages, and, as an output voltage, a voltage amplified by averaging the voltages respectively received by the first to x.sup.th input terminals with predetermined weighting ratios is output; and a selector, which, in a first selection state, supplies the output voltage to (x-m) input terminals among the first to x.sup.th input terminals, and in a second selection state, supplies the reference voltages to the (x-m) input terminals.

A digital to analog convertor comprises an output line; first, second and third pluralities of capacitors; and first and second bridge capacitors. The first plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a first least significant bit capacitor of a first capacitance value. The second plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a second capacitor of the first capacitance value. The third plurality of capacitors is coupled in parallel with one another, coupled with the output line, and comprises a third capacitor of the first capacitance value. The first bridge capacitor bridges the output line between the first plurality of capacitors and the second plurality of capacitors. The second bridge capacitor bridges the output line between the second plurality of capacitors and the third plurality of capacitors.

Superconductor analog-to-digital converters (ADC) offer high sensitivity and large dynamic range. One approach to increasing the dynamic range further is with a subranging architecture, whereby the output of a coarse ADC is converted back to analog and subtracted from the input signal, and the residue signal fed to a fine ADC for generation of additional significant bits. This also requires a high-gain broadband linear amplifier, which is not generally available within superconductor technology. In a preferred embodiment, a distributed digital fluxon amplifier is presented, which also integrates the functions of integration, filtering, and flux subtraction. A subranging ADC design provides two ADCs connected with the fluxon amplifier and subtractor circuitry that would provide a dynamic range extension by about 30-35 dB.