Improved mechanisms for applying noise-shaped segmentation techniques in a multi-bit DAC are disclosed. Noise-shaped segmentation refers to constructing two or more noise-shaped signals whose sum equals the original digital input signal by splitting each word of the input signal into two or more sub-words and converting each sub-word by a respective sub-word DAC group. Disclosed mechanisms include determining a range of amplitudes of a portion of the input signal over a certain time period, and, when converting digital words of that portion to analog values, limiting the number of sub-word DAC groups which are used for the conversion only to a number that is necessary for generating an analog output corresponding to the portion being evaluated, which number is determined based on the tracked amplitudes and could be smaller than the total number of sub-word DAC groups. Placing unused sub-word DAC groups into a power saving mode reduces power consumption.

A digital-to-analog conversion circuit, a data driver including the same, and a display device are provided. The circuit includes: a reference voltage generation part, generating a reference voltage group having different voltage values; a decoder, selecting and outputting multiple reference voltages with overlapping from the reference voltage group based on the digital data signal; an amplification circuit, where m (m being an integer of 1 or more and less than x) of first to x.sup.th input terminals respectively receive m of multiple reference voltages, and, as an output voltage, a voltage amplified by averaging the voltages respectively received by the first to x.sup.th input terminals with predetermined weighting ratios is output; and a selector, which, in a first selection state, supplies the output voltage to (x-m) input terminals among the first to x.sup.th input terminals, and in a second selection state, supplies the reference voltages to the (x-m) input terminals.

Disclosed in some examples are systems, methods, devices, and machine-readable mediums for improved communications between a software-defined radio front-end device and a network-based computing device. Rather than packetize samples together, same bit positions from multiple ADC samples may be packetized together. If a Quality of Service (QoS) metric of the network connection between the RF front-end device and the network-based processing computing drops below a threshold, the RF front-end device may prioritize sending packets with the more significant bits over packets with less significant bits. In other examples, the RF front-end device may prioritize samples corresponding to certain data types over other data types.

Disclosed in some examples are systems, methods, devices, and machine-readable mediums for improved communications between a software-defined radio front-end device and a network-based computing device. Rather than packetize samples together, same bit positions from multiple ADC samples may be packetized together. If a Quality of Service (QoS) metric of the network connection between the RF front-end device and the network-based processing computing drops below a threshold, the RF front-end device may prioritize sending packets with the more significant bits over packets with less significant bits. In other examples, the RF front-end device may prioritize samples corresponding to certain data types over other data types.

A semiconductor circuit includes first and second DA converters which selects first and second reference voltages in response to upper m bits of input digital data, a select circuitry which outputs first to N-th selected input voltages in response to lower n bits of the input digital data; first to N-th differential input stages, an output stage and a first tail current source. Each of the first to N-th differential input stages includes a transistor pair. The i-th selected input voltage is supplied to the gates of a first MISFET of the i-th differential input stage and the gates of the second MISFETs of the first to N-th differential input stages are connected to the output node. The first tail current source controls the current levels of the first tail current in the first to N-th differential input stages in response to lower n bits of the input digital data.

A semiconductor device in which variations are controlled is provided. The semiconductor device has a function of converting a digital signal into an analog signal, and includes a digital-analog converter circuit, an amplifier circuit, first to fourth switches, a first output terminal, a second output terminal, and a power source. The amplifier circuit is configured to perform feedback control when the first switch and the fourth switch are on and the second switch and the third switch are off. The amplifier circuit is configured to perform comparison control when the first switch and the fourth switch are off and the second switch and the third switch are on; utilizing this, variations in the digital-analog converter circuit and the amplifier circuit are controlled.

Disclosed are an audio ADC for supporting voice wake-up and an electronic device. The audio ADC includes a programmable gain amplifier (PGA) having an input terminal for receiving an audio signal; a bypass switch having an input terminal for receiving an analog audio signal; and a successive approximation ADC having input terminals respectively connected to output terminals of the PGA and the bypass switch; the PGA gains and amplifies the audio signal, the bypass switch bypasses the PGA, and outputs the analog audio signal; the successive approximation performs analog-to-digital conversion with noise shaping on the analog audio signal after gain amplification at a first sampling rate/oversampling rate when the audio ADC is normal working, and turns off noise shaping when the audio ADC is sleep, performs analog-to-digital conversion on the analog audio signal output by the bypass switch at a second sampling rate/oversampling rate, and outputs to a DSP.

Provided is a current output circuit 1 including a pseudo sine wave separation circuit 11 that separates a pseudo sine wave represented by a digital code Din into two pseudo half-waves represented by digital signals D1 and D2, a DA converter 113 that converts the pseudo half-wave represented by the digital signal D1 into an analog half-wave signal V1, a DA converter 114 that converts the pseudo half-wave represented by the digital signal D2 into an analog half-wave signal V2, and a voltage-current conversion circuit 12 that converts voltages of the half-wave signals V1 and V2 into currents and outputs a current Iout obtained by combining the currents.

Provided is a current output circuit 1 including a pseudo sine wave separation circuit 11 that separates a pseudo sine wave represented by a digital code Din into two pseudo half-waves represented by digital signals D1 and D2, a DA converter 113 that converts the pseudo half-wave represented by the digital signal D1 into an analog half-wave signal V1, a DA converter 114 that converts the pseudo half-wave represented by the digital signal D2 into an analog half-wave signal V2, and a voltage-current conversion circuit 12 that converts voltages of the half-wave signals V1 and V2 into currents and outputs a current Iout obtained by combining the currents.

An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.