An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.

A digital-to-analog converter (DAC) system preferably includes one or more optical modulators and can optionally include one or more electronic DAC arrays. A method for digital-to analog conversion preferably includes receiving digital inputs and providing analog optical outputs. The method for digital-to analog conversion is preferably performed using the DAC system.

An optical receiver device includes a boost converter circuit, an optical receiver circuit, and a pulse width modulation controller circuitry. The boost converter circuit is configured to convert a supply voltage according to a pulse width modulation signal, in order to generate an output voltage. The optical receiver circuit is configured to set a gain according to the output voltage, in order to convert an optical signal to a data signal according to the gain. The pulse width modulation controller circuitry is configured to perform a digital to analog conversion according to a control code to gradually adjust a current associated with the output voltage, and to compare the output voltage with a reference voltage to generate the pulse width modulation signal.

Methods and apparatus for adaptively generating a reference voltage (V.sub.REF) for biasing a switch driver and corresponding switch in a digital-to-analog converter (DAC). The adaptive biasing scheme may be capable of tracking process, voltage, and temperature (PVT) of the DAC. An example DAC generally includes a plurality of DAC cells, each DAC cell comprising a current source, a switch coupled in series with the current source, and a switch driver coupled to a control input of the switch, the switch driver being configured to receive power from a first power supply rail referenced to a reference potential node; a regulation circuit comprising a first transistor coupled between the reference potential node for the DAC and the switch driver in at least one of the plurality of DAC cells; and a V.sub.REF generation circuit coupled to the regulation circuit and configured to adaptively generate a V.sub.REF for the regulation circuit.

A high-voltage (HV) power supply outputs an output voltage based on a control signal produced by a dual analog/digital feedback loop. The control signal is determined at least in part by an error amplifier that receives a measurement signal, proportionally attenuated from the output voltage, and a digital-to-analog converter (DAC) output signal. An analog-to-digital converter (ADC) also receives the measurement signal and transmits it in digitized form to a digital processor. The digital processor calculates a digital DAC data signal based on the measurement signal, and on a digital set-point input signal corresponding to a set-point voltage value of the output voltage desired to be outputted from the high-voltage source. A DAC receives the DAC data signal and converts it to the DAC output signal transmitted to the error amplifier.

An apparatus includes a digital-to-analog converter coupled in series with a source follower, wherein the digital-to-analog converter is configured to control a current flowing through the source follower, and an amplifier having a first input coupled to a reference generator, a second input coupled to a common node of the source follower and the digital-to-analog converter, and an output coupled to a gate of the source follower.

A method of Vernier digital-to-analog conversion, the method including: performing conversion of a reference signal Y using a control code X=M+α.sup.−αN with a length ψ=α+β, wherein M is a control code with a length α, including high-order bits of the control code X, and α.sup.−αN is a control code with a length β, including lower-order bits of the control code X, wherein α≈β; performing digital multiplication of the lower-order a.sup.−αN bits of the control code X by a.sup.α times algebraic summing α of the high-order bits of the control code X and β of the lower-order bits of a.sup.−αN of the control code X being a result of multiplication by a.sup.α times, according to formula Q=M±N, wherein Nis a resulting digital code of the digital multiplication, and Q is a resulting digital code of M±N; converting the resulting digital code Q from a reference signal Y.sub.1 to an analog signal Z.sub.1, and converting the resulting digital code N from a reference signal Y.sub.2 to an analog signal Z.sub.2, wherein reference signals Y.sub.1 and Y.sub.2 are related by a ratio: Y.sub.2=Y.sub.1(1±a.sup.−α), wherein a is a base of number system, α is a number of bits of shifting the control code a.sup.−αN; and summing analog signals Z.sub.1 and Z.sub.2 to generate an analog output signal Z.sub.0.

A method of Vernier digital-to-analog conversion, the method including: performing conversion of a reference signal Y using a control code X=M+α.sup.−αN with a length ψ=α+β, wherein M is a control code with a length α, including high-order bits of the control code X, and α.sup.−αN is a control code with a length β, including lower-order bits of the control code X, wherein α≈β; performing digital multiplication of the lower-order a.sup.−αN bits of the control code X by a.sup.α times algebraic summing α of the high-order bits of the control code X and β of the lower-order bits of a.sup.−αN of the control code X being a result of multiplication by a.sup.α times, according to formula Q=M±N, wherein Nis a resulting digital code of the digital multiplication, and Q is a resulting digital code of M±N; converting the resulting digital code Q from a reference signal Y.sub.1 to an analog signal Z.sub.1, and converting the resulting digital code N from a reference signal Y.sub.2 to an analog signal Z.sub.2, wherein reference signals Y.sub.1 and Y.sub.2 are related by a ratio: Y.sub.2=Y.sub.1(1±a.sup.−α), wherein a is a base of number system, α is a number of bits of shifting the control code a.sup.−αN; and summing analog signals Z.sub.1 and Z.sub.2 to generate an analog output signal Z.sub.0.

A segmented digital-to-analog converter (DAC) includes DAC segments, an overrange DAC, and a dither control circuit. Each DAC segment includes a plurality of DAC cells for generating an analog output signal based on input data to each DAC segment. The overrange DAC generates an analog output signal based on a control signal. The dither control circuit adds a dither to first input data supplied to a higher-order DAC segment, subtract a portion of the dither from second input data supplied to a lower-order DAC segment, and generate the control signal for subtracting a remaining portion of the dither from an output of the segmented DAC in an analog domain. The dither added to the first input data may be one of +1, 0, and −1 and the portion of the dither subtracted from the second input data may be a half of the dither added to the first input data.

A digital-to-analog conversion circuit includes: a decoder that, if set to a first selection state, selects two different reference voltages from a reference voltage group on the basis of a digital data signal and outputs the two reference voltages as first and second selection voltages, and if set to a second selection state, selects two reference voltages from the reference voltage group in a manner allowing redundancy and outputs the two reference voltages as the first and second selection voltages; and an amplifier circuit that amplifies and outputs a voltage obtained by averaging a combination of the first and second selection voltages with weighting factors set in advance.