A digital-to-analog conversion, including: converting signal Y using word X=M+a.sup.−aN having length Ψ=α+β digits, where M is high order digits of a long control word X, a.sup.−aN is low order digits of β long control word X, wherein α≈β; subjecting analog signal Z to three conversions, wherein, in the first conversion, signal Z.sub.1 is proportional to Mα long high order digits of X, and to reference signal Y.sub.1, where Z.sub.1=Y.sub.1×M, in the second and third conversions, signals Z.sub.2 and Z.sub.3 are proportional to Nβ long low order digits of X and to signals Y.sub.1 and Y.sub.2, respectively, where Z.sub.2=Y.sub.1×N, and Z.sub.3=Y.sub.2×N, wherein, before the conversions, a.sup.−aN low order digits of X are multiplied by a.sup.a; and adding Z.sub.1, Z.sub.2, Z.sub.3 to generate output signal Z.sub.0, wherein Y.sub.1 and Y.sub.2 relate by Y.sub.2=Y.sub.1(1±a.sup.−a), wherein a is the base of the numbering system, α is the number of digits, by which a.sup.−aN is shifted.

A digital-to-analog conversion, including: converting signal Y using word X=M+a.sup.−aN having length Ψ=α+β digits, where M is high order digits of a long control word X, a.sup.−aN is low order digits of β long control word X, wherein α≈β; subjecting analog signal Z to three conversions, wherein, in the first conversion, signal Z.sub.1 is proportional to Mα long high order digits of X, and to reference signal Y.sub.1, where Z.sub.1=Y.sub.1×M, in the second and third conversions, signals Z.sub.2 and Z.sub.3 are proportional to Nβ long low order digits of X and to signals Y.sub.1 and Y.sub.2, respectively, where Z.sub.2=Y.sub.1×N, and Z.sub.3=Y.sub.2×N, wherein, before the conversions, a.sup.−aN low order digits of X are multiplied by a.sup.a; and adding Z.sub.1, Z.sub.2, Z.sub.3 to generate output signal Z.sub.0, wherein Y.sub.1 and Y.sub.2 relate by Y.sub.2=Y.sub.1(1±a.sup.−a), wherein a is the base of the numbering system, α is the number of digits, by which a.sup.−aN is shifted.

An apparatus and method are disclosed with some embodiments including an analog and time to digital converter (ATDC) including a receiver, the receiver for receiving an analog channel input for conversion to a digital data, the digital data having at least one bit, and a defined absolute reference time stamp, the defined absolute reference time stamp representing an absolute reference time associated with conversion of the analog channel input to the digital data and an analog-to-digital converter, the converter converting the analog channel input to the digital data.

An example apparatus includes: a voltage-to-current circuit including a first input terminal, a first output terminal and a second output terminal, a subtraction circuit including a second input terminal and a third output terminal, the second input terminal coupled to the second output terminal, a first driver circuit including a third input terminal and a fourth output terminal, the third input terminal coupled to the third output terminal, and a second driver circuit including a fourth input terminal and a fifth output terminal, the fourth input terminal coupled to the first output terminal, the fifth output coupled to the fourth output terminal.

A current-mode circuit, comprising: at least one switch unit, each switch unit comprising a field-effect transistor connected at its source terminal in series with an impedance and configured to carry a given current, wherein for each switch unit or for at least one of the switch units the impedance is a variable impedance; and an adjustment circuit configured, for each switch unit or for said at least one of the switch units, to adjust an impedance of the variable impedance to calibrate a predetermined property of the switch unit which is dependent on the field-effect transistor.

A reference voltage generator comprises a comparator, a digital-to-analog converter (DAC) and a switched capacitor accumulator. The comparator receives a reference voltage input, a feedback input, and a control signal. The DAC is coupled to an output of the comparator, and the switched capacitor accumulator is coupled to an output of the DAC. In some implementations, a digital filter is coupled between the output of the comparator and the input of the DAC. The switched capacitor accumulator can be coupled to a buffer that outputs the feedback input and a reference voltage for an analog-to-digital converter (ADC). In some implementations, the feedback loop includes N one-bit DACs coupled to the output of the comparator and N switched capacitor accumulators, each of which is coupled to a unique one-bit DAC.

A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal. However, while each unit cell may be generally the same, there may be variations such as non-linearity or noise in the analog output depending on which unit cells are activated for a given digital signal value. For example, as additional unit cells are activated for increased values of the analog signal, the fill order in which the unit cells are activated may affect the linearity/noise of the DAC. The decision units may be programmable to select which branches of the fractal DAC to activate, changing the fill order based on a fill-selection signal. The fill order may be set by a fill controller via the fill-selection signal to account for manufacturing variations, gradients in the supply voltage, output line routing, and/or environmental factors such as temperature.

A number of unit cells of a digital-to-analog converter (DAC) may be simultaneously activated to generate an analog signal. However, while each unit cell may be generally the same, there may be variations such as non-linearity or noise in the analog output depending on which unit cells are activated for a given digital signal value. For example, as additional unit cells are activated for increased values of the analog signal, the fill order in which the unit cells are activated may affect the linearity/noise of the DAC. The decision units may be programmable to select which branches of the fractal DAC to activate, changing the fill order based on a fill-selection signal. The fill order may be set by a fill controller via the fill-selection signal to account for manufacturing variations, gradients in the supply voltage, output line routing, and/or environmental factors such as temperature.

Described are apparatus and methods to calibrate and align multiple high-speed clock domains. A system includes at least two clock domains, a launch circuit connected to each of the at least two domains, and a calibration circuit. Each clock domain including a resettable device having a local reset retime clock. The launch circuit aligns a reset pulse with the local reset retime clock by using a launch clock from one of the domains, where the reset pulse is incoherent with respect to the domains, adjusts a delay of the launch clock to control a launch time of the reset pulse, and sends the reset pulse based on the delayed launch clock. The calibration circuit samples a local reset retime delayed clock to generate a readback signal. The launch circuit and the calibration circuit iterate through selected delays until safe arrival timing is indicated from each readout.

Described are apparatus and methods to calibrate and align multiple high-speed clock domains. A system includes at least two clock domains, a launch circuit connected to each of the at least two domains, and a calibration circuit. Each clock domain including a resettable device having a local reset retime clock. The launch circuit aligns a reset pulse with the local reset retime clock by using a launch clock from one of the domains, where the reset pulse is incoherent with respect to the domains, adjusts a delay of the launch clock to control a launch time of the reset pulse, and sends the reset pulse based on the delayed launch clock. The calibration circuit samples a local reset retime delayed clock to generate a readback signal. The launch circuit and the calibration circuit iterate through selected delays until safe arrival timing is indicated from each readout.