A semiconductor device includes a memory cell array including a plurality of memory cells coupled between a multiplicity of word lines and one or more bit lines; and an operation circuit configured to perform a multiplication and accumulation (MAC) operation with one or more first multi-bit data provided from the one or more bit lines and one or more second multi-bit data, wherein a plurality of memory cells coupled to a bit line store a plurality of bits included in a corresponding one of the one or more first multi-bit data, and wherein the memory cell array sequentially provides the plurality of bits included in the corresponding first multi-bit data to the operation circuit.

A semiconductor device includes a memory cell array including a plurality of memory cells coupled between a multiplicity of word lines and one or more bit lines; and an operation circuit configured to perform a multiplication and accumulation (MAC) operation with one or more first multi-bit data provided from the one or more bit lines and one or more second multi-bit data, wherein a plurality of memory cells coupled to a bit line store a plurality of bits included in a corresponding one of the one or more first multi-bit data, and wherein the memory cell array sequentially provides the plurality of bits included in the corresponding first multi-bit data to the operation circuit.

Computing-in-memory utilizes memory as weight for multiply-and-accumulate (MAC) operations. Input data multiplies weights to produce output data during the operation. Method of data conversion from input data, memory element to output data is described to enhance the computing efficiency.

Differential circuitry including first and second current paths each including a succession of first and further load nodes, each successive further load node connected to its preceding load node via a divider impedance; and first switching circuitry connected to the further load node or nodes of the first current path, and second switching circuitry connected to the further load node or nodes of the second current path, the first and second switching circuitry controlling a magnitude of controllable current signals passing through the load nodes of the first current path and the second current path, respectively, wherein: the first load nodes of the first and second current paths include a first pair of load nodes, and the or each successive further load node of the first current path and its corresponding successive further load node of the second current path include a successive further pair of load nodes.

A high-order converter generates a first high-order voltage V.sub.U_P and a second high-order voltage V.sub.U_N that monotonously change with mutually opposite polarities with respect to high-order m bits (1≤m<n) of the digital signal. A low-order converter generates a first low-order voltage and a second low-order voltage that monotonously change with mutually opposite polarities with respect to low-order (n−m) bits of the digital signal. A first amplifier receives one of the first and the second high-order voltages and one of the first and the second low-order voltages to output one differential analog signal. Having a configuration in common with the first amplifier, a second amplifier receives another of the first and the second high-order voltages and another of the first and the second low-order voltages to output another differential analog signal.

A high-order converter generates a first high-order voltage V.sub.U_P and a second high-order voltage V.sub.U_N that monotonously change with mutually opposite polarities with respect to high-order m bits (1≤m<n) of the digital signal. A low-order converter generates a first low-order voltage and a second low-order voltage that monotonously change with mutually opposite polarities with respect to low-order (n−m) bits of the digital signal. A first amplifier receives one of the first and the second high-order voltages and one of the first and the second low-order voltages to output one differential analog signal. Having a configuration in common with the first amplifier, a second amplifier receives another of the first and the second high-order voltages and another of the first and the second low-order voltages to output another differential analog signal.

A digital-analog converter includes a digital-analog converter circuit connected to a first mirror current circuit that receives an additional current obtained by adding a current from a voltage-current converter circuit for generating a current according to a received voltage signal to a shift current from a shift current source and a second mirror current circuit that receives the shift current. The digital-analog converter circuit includes current switching circuits. Each current switching circuit includes a first mirror current source that provides a mirror current from one of the first and the second mirror current circuit, a second mirror current source that provides a mirror current from the other, and a switch circuit that determines whether the first and the second mirror current source of each current switching circuit contribute to a value of an analog signal at an D/A output in response to a decoded signal value.

A digital-analog converter includes a digital-analog converter circuit connected to a first mirror current circuit that receives an additional current obtained by adding a current from a voltage-current converter circuit for generating a current according to a received voltage signal to a shift current from a shift current source and a second mirror current circuit that receives the shift current. The digital-analog converter circuit includes current switching circuits. Each current switching circuit includes a first mirror current source that provides a mirror current from one of the first and the second mirror current circuit, a second mirror current source that provides a mirror current from the other, and a switch circuit that determines whether the first and the second mirror current source of each current switching circuit contribute to a value of an analog signal at an D/A output in response to a decoded signal value.

Digital-to-analog converters (DACs) having a multiple-gate (multi-gate) transistor-like structure are disclosed herein. The DAC structures have a similar structure to a transistor (e.g., a MOSFET) and include source and drain regions. However, instead of employing only one gate between the source and drain regions, multiple distinct gates are employed. Each distinct gate can represent a bit for the DAC and can include different gate lengths to enable providing different current values, and thus, unique outputs. Further, N number of inputs can be applied to N number of gates employed by the DAC. The DAC structure may be configured such that the longest gate controls the LSB of the DAC and the shortest gate controls the MSB, or vice versa. In some cases, the multi-gate DAC employs high-injection velocity materials that enable compact design and routing, such as InGaAs, InP, SiGe, and Ge, to provide some examples.

Digital-to-analog converters (DACs) having a multiple-gate (multi-gate) transistor-like structure are disclosed herein. The DAC structures have a similar structure to a transistor (e.g., a MOSFET) and include source and drain regions. However, instead of employing only one gate between the source and drain regions, multiple distinct gates are employed. Each distinct gate can represent a bit for the DAC and can include different gate lengths to enable providing different current values, and thus, unique outputs. Further, N number of inputs can be applied to N number of gates employed by the DAC. The DAC structure may be configured such that the longest gate controls the LSB of the DAC and the shortest gate controls the MSB, or vice versa. In some cases, the multi-gate DAC employs high-injection velocity materials that enable compact design and routing, such as InGaAs, InP, SiGe, and Ge, to provide some examples.