An innovative low-bit-width device may include a first digital-to-analog converter (DAC), a second DAC, a plurality of non-volatile memory (NVM) weight arrays, one or more analog-to-digital converters (ADCs), and a neural circuit. The first DAC is configured to convert a digital input signal into an analog input signal. The second DAC is configured to convert a digital previous hidden state (PHS) signal into an analog PHS signal. NVM weight arrays are configured to compute vector matrix multiplication (VMM) arrays based on the analog input signal and the analog PHS signal. The NVM weight arrays are coupled to the first DAC and the second DAC. The one or more ADCs are coupled to the plurality of NVM weight arrays and are configured to convert the VMM arrays into digital VMM values. The neural circuit is configured to process the digital VMM values into a new hidden state.

Computing-in-memory utilizes memory as weight for multiply-and-accumulate (MAC) operations. Input data multiplies weights to produce output data during the operation. Method of data conversion from input data, memory element to output data is described to enhance the computing efficiency.

A digital-to-analog conversion, including: converting signal Y using word X=M+α.sup.−αN having length Ψ=α+β digits, where M is high order digits of α long control word X, α.sup.−αN is low order digits of β long control word X, wherein α≈β; subjecting analog signal Z to three conversions, wherein, in the first conversion, signal Z.sub.1 is proportional to Mα long high order digits of X, and to reference signal Y.sub.1, where Z.sub.1=Y.sub.1×M, in the second and third conversions, signals Z.sub.2 and Z.sub.3 are proportional to Nβ long low order digits of X and to signals Y.sub.1 and Y.sub.2, respectively, where Z.sub.2=Y.sub.1×N, and Z.sub.3=Y.sub.2×N, wherein, before the conversions, α.sup.−αN low order digits of X are multiplied by α.sup.α; and adding Z.sub.1, Z.sub.2, Z.sub.3 to generate output signal Z.sub.0, wherein Y.sub.1 and Y.sub.2 relate by Y.sub.2=Y.sub.1(1±α.sup.−α), wherein α is the base of the numbering system, α is the number of digits, by which α.sup.−αN is shifted.

A digital-to-analog conversion, including: converting signal Y using word X=M+α.sup.−αN having length Ψ=α+β digits, where M is high order digits of α long control word X, α.sup.−αN is low order digits of β long control word X, wherein α≈β; subjecting analog signal Z to three conversions, wherein, in the first conversion, signal Z.sub.1 is proportional to Mα long high order digits of X, and to reference signal Y.sub.1, where Z.sub.1=Y.sub.1×M, in the second and third conversions, signals Z.sub.2 and Z.sub.3 are proportional to Nβ long low order digits of X and to signals Y.sub.1 and Y.sub.2, respectively, where Z.sub.2=Y.sub.1×N, and Z.sub.3=Y.sub.2×N, wherein, before the conversions, α.sup.−αN low order digits of X are multiplied by α.sup.α; and adding Z.sub.1, Z.sub.2, Z.sub.3 to generate output signal Z.sub.0, wherein Y.sub.1 and Y.sub.2 relate by Y.sub.2=Y.sub.1(1±α.sup.−α), wherein α is the base of the numbering system, α is the number of digits, by which α.sup.−αN is shifted.

A method for outputting a current includes performing a sorting operation on a plurality of current sources according to intensities of currents generated by the current sources, dividing the plurality of current sources into N current source sets according to a result of the sorting operation and a predetermined selection order, and enabling at least one current source set of the N current source sets to output the current according a target output value. The plurality of current sources have a same target current value. Each of the N current source sets includes at least one current source. In the N current source sets, a total quantity of current sources of the n.sup.th current source set is twice a total quantity of current sources of the (n−1).sup.th current source set.

A digital-to-analog conversion circuit includes a first digital-to-analog converter (DAC) and a second DAC. The first DAC includes a first current generation circuit (CGC) and a first current-to-voltage converter. The first CGC generates a first current based on a first digital code received through a first terminal to provide the first current to an output node. The second DAC includes a second CGC and a second current-to-voltage converter. The second CGC generates a second current based on a second digital code received through a second input terminal to provide the second current to the output node. The first current-to-voltage converter and the second current-to-voltage converter convert a sum of the first current and the second current to a an analog voltage corresponding to a sum of the first digital code and the second digital code, and output the analog voltage at the output node.

A semiconductor circuit and a method of operating the same are provided. The semiconductor circuit comprises a first digital-to-analog converter configured to generate a first output current in response to a first binary code, and a second digital-to-analog converter configured to generate a second output current in response to a second binary code associated with the first binary code. The semiconductor circuit further comprises a first current-to-voltage converter configured to generate a first candidate voltage based on the first output current, and a second current-to-voltage converter configured to generate a second candidate voltage based on the second output current. The semiconductor circuit further comprises a multiplexer configured to output the target voltage based on the first candidate voltage or the second candidate voltage. The target voltage includes a configurable range associated with the second binary code.

Certain aspects of the present disclosure provide a digital-to-analog converter (DAC) system. The DAC system generally includes a plurality of current steering cells, each comprising a current source coupled to at least two current steering switches, wherein control inputs of the at least two current steering switches are coupled to an input path of the DAC system. The DAC system may also include a current source toggle circuit configured to selectively disable the current source of at least one of the plurality of current steering cells, and a feedforward path coupled between the input path and at least one control input of the current source toggle circuit.

The systems and methods discussed herein utilized a wireless or wired transceiver having a transmitter and a receiver. The transceiver is configured to reduce distortion contributions associated with echo cancelling. The transmitter provides a replica signal and a transmit signal. The replica signal and the transmit signal can be provided using a common switch.

Described herein are systems and methods that can adjust the performance of a transimpedance amplifier (TIA) in order to compensate for changing environmental and/or manufacturing conditions. In some embodiments, the changing environmental and/or manufacturing conditions may cause a reduction in beta of a bipolar junction transistor (BJT) in the TIA. A low beta may result in a high base current for the BJT causing the output voltage of the TIA to be formatted as an unusable signal output. To compensate for the low beta, the TIA generates an intermediate signal voltage, based on the base current and beta that is compared with the PN junction bias voltage on another BJT. Based on the comparison, the state of a digital state machine may be incremented, and a threshold base current is determined. This threshold base current may decide whether to compensate the operation of the TIA, or discard the chip.