An electronic device may include digital circuitry to operate via digital signals and analog circuitry to operate via analog signals. The electronic device may also include a fractal digital to analog converter (DAC) to convert a digital signal into an analog signal. The fractal DAC may include a unit cell array having a branching data path and multiple unit cells disposed in a fractal pattern. The fractal DAC may also include multiple decision units disposed within the unit cell array on the branching data path. Each decision unit may receive an incoming signal representative of at least a portion of the digital signal and direct each decision unit output to different branches of the unit cell array. The unit cells may be enabled based at least in part on the decision unit outputs to generate the analog signal.

An electronic device may include digital circuitry to operate via digital signals and analog circuitry to operate via analog signals. The electronic device may also include a fractal digital to analog converter (DAC) to convert a digital signal into an analog signal. The fractal DAC may include a unit cell array having a branching data path and multiple unit cells disposed in a fractal pattern. The fractal DAC may also include multiple decision units disposed within the unit cell array on the branching data path. Each decision unit may receive an incoming signal representative of at least a portion of the digital signal and direct each decision unit output to different branches of the unit cell array. The unit cells may be enabled based at least in part on the decision unit outputs to generate the analog signal.

An imaging device according to an embodiment of the present disclosure includes: a plurality of current sources including first group current sources and second group current sources; and a control unit that controls driving of the first group current sources to generate a first-phase ramp voltage and controls driving of the first group current sources and at least one current source of the second group current sources to generate a second-phase ramp voltage.

A digital-to-analog converter includes a plurality of 1-bit elements each of which outputs a current corresponding to a value indicated by a digital signal when the digital signal is input; and a capacitive load connected to the plurality of 1-bit elements, the digital-to-analog converter being configured to generate an analog voltage waveform via the capacitive load that receives currents output from the plurality of 1-bit elements, wherein each of the 1-bit elements includes a switching circuit to change a bias of a voltage in each of the 1-bit elements according to a value indicated by an input digital signal, and to switch connection and non-connection with a power supply according to a change in the bias.

Embodiments of this application provide example digital-to-analog converters and electronic devices, and relate to the field of electronic technologies. The digital-to-analog converter includes a current source array and a switch array, and the current source array includes a plurality of active current source units. A metal is filled above the plurality of active current source units. The switch array includes a plurality of switch units. Control ends of the plurality of switch units are configured to receive control signals, and input ends of the plurality of switch units are respectively configured to receive corresponding currents provided by the plurality of active current source units. Output ends of the plurality of switch units are coupled to an output end of the digital-to-analog converter, and are configured to output analog signals.

Embodiments of this application provide example digital-to-analog converters and electronic devices, and relate to the field of electronic technologies. The digital-to-analog converter includes a current source array and a switch array, and the current source array includes a plurality of active current source units. A metal is filled above the plurality of active current source units. The switch array includes a plurality of switch units. Control ends of the plurality of switch units are configured to receive control signals, and input ends of the plurality of switch units are respectively configured to receive corresponding currents provided by the plurality of active current source units. Output ends of the plurality of switch units are coupled to an output end of the digital-to-analog converter, and are configured to output analog signals.

An imaging device according to an embodiment of the present disclosure includes: a plurality of current sources including first group current sources and second group current sources; and a control unit that controls driving of the first group current sources to generate a first-phase ramp voltage and controls driving of the first group current sources and at least one current source of the second group current sources to generate a second-phase ramp voltage.

An in-memory computation circuit includes a memory array including sub-arrays of with SRAM cells connected in rows by word lines and in columns by bit lines. A row controller circuit selectively actuates word lines across the sub-arrays for an in-memory compute operation. A computation tile circuit for each sub-array includes a column compute circuit for each bit line. Each column compute circuit includes a switched timing circuit that is actuated in response to weight data on the bit line for a duration of time set by an in-memory compute operation enable signal. A current digital-to-analog converter powered by the switched timing circuit operates to generate a drain current having a magnitude controlled by bits of feature data for the in-memory compute operation. The drain current is integrated to generate an output voltage.

A solid-state imaging device configured to suppress fixed pattern noise having column correlation and/or lateral correlation from being generated in images is disclosed. In one example, a solid-state imaging device includes unit pixels arranged in row and column directions, vertical signal lines respectively connected to at least one of the unit pixels arranged in the column direction, first converters connected to the respective vertical signal lines and configured to convert an analog pixel signal into a digital pixel signal in reading each unit pixel arranged in the row direction, an initialization voltage generator that outputs an initialization voltage for initializing the unit pixels or input nodes of the first converters, and an initialization voltage line that connects the initialization voltage generator and the first converters. The initialization voltage generator changes the initialization voltage that is output for each row and/or column to be processed by the first converters.

A method for outputting a current includes performing a sorting operation on a plurality of current sources according to intensities of currents generated by the current sources, dividing the plurality of current sources into N current source sets according to a result of the sorting operation and a predetermined selection order, and enabling at least one current source set of the N current source sets to output the current according a target output value. The plurality of current sources have a same target current value. Each of the N current source sets includes at least one current source. In the N current source sets, a total quantity of current sources of the n.sup.th current source set is twice a total quantity of current sources of the (n−1).sup.th current source set.