Techniques regarding error detection in one or more generated signals based on one or more signal-to-noise ratios are provided. For example, one or more embodiments described herein can include a system, which can include a memory that can store computer executable components. The system can also include a processor, operably coupled to the memory, and that can execute the computer executable components stored in the memory. The computer executable components can include a signal analysis component that can determine a signal-to-noise ratio associated with a generated signal, wherein the signal-to-noise ratio incorporates a signal value based on a reference signal and a noise value based on a difference between the reference signal and an acquired signal.

A wave-generation circuit is provided. A core circuit establishes digital data. A fetch and calculation circuit generates a first data string and a second data string according to the digital data, outputs the first data string via a first pin, and outputs the second data string via a second pin. A latch circuit latches the first and second data strings. The latch circuit uses the first data string as first input data, and use the second data string as second input data. A digital-to-analog conversion circuit receives and converts the first input data and the second input data to generate a first output wave and a second output wave. After the core circuit establishes the digital data, the fetch and calculation circuit, the latch circuit, and the digital-to-analog conversion circuit operate independently of the core circuit to generate the first output wave and the second output wave.

A column analog-to-digital converter and the local counting method is provided. The column analog-to-digital converter includes a plurality of analog-to-digital converters in parallel. Each of the analog-to-digital converters includes a comparator and a counting circuit. The comparator compares the ramp voltage with one of the plurality of column signals to generate a comparator output signal. The counting circuit generates a local clock by means of a voltage-controlled oscillator of the counting circuit according to the base clock and the comparator output signal, counts the base clock and the local clock respectively to generate a first counting output and a second counting output, and combines the first counting output with the second counting output to generate the counting output.

A method for checking a message in a communication system, in which multiple users are connected to a communication medium that includes two signal lines and exchange messages via same. A time difference between points in time of reception of a message that is sent on the communication medium is ascertained at two different, predefined positions on the communication medium, and based on a comparison of the time difference to at least one reference time difference, it is determined whether the message originates from a verified user. During the ascertainment of the time difference at the two positions, in each case a difference signal is formed from signals that have resulted on the two signal lines due to the message.

A method for checking a message in a communication system, in which multiple users are connected to a communication medium that includes two signal lines and exchange messages via same. A time difference between points in time of reception of a message that is sent on the communication medium is ascertained at two different, predefined positions on the communication medium, and based on a comparison of the time difference to at least one reference time difference, it is determined whether the message originates from a verified user. During the ascertainment of the time difference at the two positions, in each case a difference signal is formed from signals that have resulted on the two signal lines due to the message.

A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

A digital-to-time converter (DTC) converts a digital code into a time delay using a capacitor digital-to-analog converter (CDAC) that functions as a charging capacitor. The DTC includes a switched capacitor voltage-to-current converter for the formation of a charging current (or a discharging current) for charging (or for discharging) the charging capacitor responsive to a triggering clock edge that begins the time delay. A comparator compares a voltage on the charging capacitor to a threshold voltage to determine an end of the time delay.

An analog-to-digital conversion circuit includes a comparator circuit configured to perform processing of comparison between an analog signal and a ramp signal, and a counter configured to perform count processing in parallel with the comparison processing by the comparator circuit. The analog-to-digital conversion circuit acquires digital data, which is a count value corresponding to the comparison processing, and subjects the analog signal to analog-to-digital conversion. A period from the start to the end of the analog-to-digital conversion of the one analog signal includes a first period and a second period following the first period. The first and the second periods are switched based on an output of the counter. The count processing is performed at a high speed during the first period and performed at a low speed during the second period.

A circuit includes a comparator configured to generate a first conversion gain output signal by comparing a first pixel signal corresponding to a first conversion gain with a first ramp signal, and generate a second conversion gain output signal by comparing a second pixel signal corresponding to a second conversion gain with a second ramp signal, and a counter configured to count pulses of the first conversion gain output signal, output a counting result as a first digital signal, and determine whether an output of a second digital signal corresponding to the second conversion gain is required, based on the first digital signal. The first conversion gain is higher than the second conversion gain, and based on determining that the output of the second digital signal is not required, the counter is further configured to control the comparator such that the second conversion gain output signal is not generated.

A frequency synthesizer includes: a time-to-digital converter configured to output a time-to-digital value corresponding to a time event of a trigger signal with respect to an operating clock signal; a comparison unit configured to compare a value based on the time-to-digital value with a target value; an oscillation unit configured to generate the synthesizer signal; and a frequency adjustment unit configured to adjust a frequency of the synthesizer signal based on a comparison result of the comparison unit. The time-to-digital converter includes: a state transition unit configured to start a state transition in which an internal state transitions based on the time event of the trigger signal and output state information indicating the internal state; a transition state acquisition unit configured to acquire and hold the state information in synchronization with the operating clock signal; and a calculation unit configured to calculate the time-to-digital value according to the number of transition times of the internal state based on the state information acquired by the transition state acquisition unit.