An input current (I.sub.in) is transformed into an output integrated voltage (V.sub.out_int) using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period (T.sub.clk_DAC) defining time intervals between successive rising edges of the feedback pulses. Sampling is performed during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (T.sub.clk_DAC).

An input current (I.sub.in) is transformed into an output integrated voltage (V.sub.out_int) using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period (T.sub.clk_DAC) defining time intervals between successive rising edges of the feedback pulses. Sampling is performed during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (T.sub.clk_DAC).

A multi-band remote unit is disclosed. The multi-hand remote unit includes a number of radio frequency (RF) front-end circuits configured to generate a number of downlink RF communications signals associated with a number of frequency bands based on a number of downlink digital communications signals, respectively. The multi-band remote unit also includes a digital interface circuit and a digital processing circuit. The digital interface circuit is configured to receive an encapsulated downlink digital communications signal and generate the downlink digital communications signals associated with the frequency bands based on the encapsulated downlink digital communications signal. The digital processing circuit is configured to digitally process the downlink digital communications signals before providing the downlink digital communications signals to the RF front-end circuits. As such, it may be possible to share the digital processing circuit among RF front-end circuits, thus helping to reduce cost and/or power consumption of the multi-band remote unit.

A multi-band remote unit is disclosed. The multi-hand remote unit includes a number of radio frequency (RF) front-end circuits configured to generate a number of downlink RF communications signals associated with a number of frequency bands based on a number of downlink digital communications signals, respectively. The multi-band remote unit also includes a digital interface circuit and a digital processing circuit. The digital interface circuit is configured to receive an encapsulated downlink digital communications signal and generate the downlink digital communications signals associated with the frequency bands based on the encapsulated downlink digital communications signal. The digital processing circuit is configured to digitally process the downlink digital communications signals before providing the downlink digital communications signals to the RF front-end circuits. As such, it may be possible to share the digital processing circuit among RF front-end circuits, thus helping to reduce cost and/or power consumption of the multi-band remote unit.

Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.

Modulation circuitry is configured to generate a phase modulated signal having an output frequency that corresponds to a local oscillator (LO) signal divided by N.5. A phase locked loop (PLL) is configured to generate an LO signal having a frequency that is N.5 times the output frequency. Pulse circuitry configured to generate, based at least on a value of N, an edge signal including a pulse aligned with a positive edge of the LO signal and a pulse aligned with a negative edge of the LO signal. The edge signal is used to generate the phase modulated signal.

An input current (I.sub.in) is transformed into an output integrated voltage (V.sub.out_int) using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period (T.sub.clk_DAC) defining time intervals between successive rising edges of the feedback pulses. Sampling is performed during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (T.sub.clk_DAC).

An input current (I.sub.in) is transformed into an output integrated voltage (V.sub.out_int) using a parallel connection of an operational transconductance amplifier and an integration capacitor. The output integrated voltage is reduced by repeatedly discharging the integration capacitor through a feedback loop via a digital-to-analog converter generating feedback pulses, a feedback clock period (T.sub.clk_DAC) defining time intervals between successive rising edges of the feedback pulses. Sampling is performed during an extended feedback clock period (T*) after a lapse of a plurality of feedback clock periods (T.sub.clk_DAC).

CDAC (Capacitive DAC (Digital-to-Analog Converter) unit cells and RFDACs (Radio Frequency DACs) employing such CDAC unit cells are disclosed that can be employed for mmWave (millimeter wave) communication are disclosed. One example CDAC unit cell comprises: four capacitors connected in pairs to two differential outputs of the CDAC unit cell; and four logic gates, wherein each logic gate of the four logic gates is configured to receive an associated clock signal of four different clock signals and an associated enable signal of four different enable signals, and wherein each logic gate of the four logic gates is configured to trigger an associated pulse from an associated capacitor of the four capacitors based on the associated clock signal and the associated enable signal of that logic gate.

CDAC (Capacitive DAC (Digital-to-Analog Converter) unit cells and RFDACs (Radio Frequency DACs) employing such CDAC unit cells are disclosed that can be employed for mmWave (millimeter wave) communication are disclosed. One example CDAC unit cell comprises: four capacitors connected in pairs to two differential outputs of the CDAC unit cell; and four logic gates, wherein each logic gate of the four logic gates is configured to receive an associated clock signal of four different clock signals and an associated enable signal of four different enable signals, and wherein each logic gate of the four logic gates is configured to trigger an associated pulse from an associated capacitor of the four capacitors based on the associated clock signal and the associated enable signal of that logic gate.