A modulator including a delta-sigma modulation circuit having an order greater than 1, and configured to modulate an input signal into a Pulse Density Modulated (PDM) signal; and a Pad Asymmetric Compensation (PAC) circuit configured to linearize a relation between a magnitude of the input signal and a number of rise or fall transitions of the PDM signal by maximizing the number of rise or fall transitions of the PDM signal, and to output a modified PDM signal, wherein the linearized relation is for compensating for any offset in the PDM signal.

Techniques for a configurable analog-to-digital converter filter to ameliorate transfer function peaking or frequency response issues are provided. In an example, a front-end circuit of a processing circuit can include a resistor-capacitor filter including at least two capacitors and a switch circuit. The resistor-capacitor filter can couple an input analog signal to the processing circuit. The switch circuit can couple to a first capacitor of the at least two capacitors, and can selectively place a terminal of the first capacitor at a selected one of a plurality of distinct nodes of the resistor-capacitor filter to configure the circuit to address the peaking or frequency response issue.

An ultrasound device is describe in which analog ultrasonic transducer output signal are directly converted to digital signals. The ultrasound device includes microfabricated ultrasonic transducers directly coupled to a sigma delta analog-to-digital converter in some instances. The direct digital conversion may allow for omission of undesirable analog processing stages in the ultrasound circuitry chain. In some situations, the ADC may be integrated on the same substrate as the ultrasound transducer.

A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal, a first summing junction configured to subtract a feedback analog signal from the input analog signal, a loop filter configured to filter an output signal from the first summing junction: an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC includes multiple per-bit parallel loops, each loop configured to provide a per-bit current summation of the filtered analog output signal such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal.

A method and apparatus for temperature compensation for data converters in a software defined radio. Specifically, the system and method are teach monitoring the temperature of critical signal processing components such as band pass filters, ADCs and DACs and retrieving modulator coefficients in response to the temperatures and the like. The modulator coefficients are then used to compensate for temperature changes, performance changes and the like.

A delta-sigma modulation type A/D converter includes: a capacitively coupled amplifier having a sampling capacitor, a feedback capacitor, and an amplifier; a correlated double sampling type first integrator as a first-stage integrator, which is connected to the capacitively coupled amplifier without a switch; a second integrator arranged after the first integrator; a quantizer arranged after the second integrator and quantizing an output of the second integrator; and an D/A converter that D/A-converts an output of the quantizer and feeds back to any one of the capacitively coupled amplifier, the first integrator, and the second integrator.

Disclosed are a sigma-delta modulator that directly converts a current signal into digital data, an ADC utilizing the sigma-delta modulator, and a neural network computing system utilizing the ADC. The sigma-delta modulator includes: a delta circuit to generate a differential current between an analog current signal output from a resistive memory and a first current included in the analog current signal, the first current having an amount of current determined by a digital modulation signal; an integration circuit to generate an integration current by integrating the differential current; and a quantization circuit to generate the digital modulation signal corresponding to the integration current. The sigma-delta modulator can minimize the generation of noise by using no capacitor that performs a function by a switch, and can increase a signal processing speed for conversion by allowing the signal processing speed to be determined by a signal processing speed of one element.

The invention describes a method of performing analog-to-digital conversion on an input signal (P.sub.in) within a range (R1) using a sigma-delta modulator (1) comprising a feedback digital-to-analog conversion arrangement (12, 120), which method comprises the steps of: obtaining an amplitude estimate (E1, E2, E3, E4) of the input signal (P.sub.in); defining a subsequent subrange (R2, R3, R4) on the basis of the amplitude estimate (E1, E2, E3); and adjusting operation parameters of the feedback digital-to-analog conversion arrangement (12, 120) on the basis of the subsequent subrange (R2, R3, R4); whereby the method steps are repeated a predefined number of iterations (N). The invention further describes a sigma-delta modulator (1), an analog-to-digital converter (50), and a monitoring device (5) for monitoring an analog input signal (P.sub.in).

Circuits and methods for inter-symbol interference compensation are described. These circuits and methods may be used in connection with delta-sigma analog-to-digital converter. During a sensing phase, a value indicative of the inter-symbol interference may be sensed. The value may be obtained by (1) causing the ADC to generate a first number of transitions during a first time interval; (2) causing the ADC to generate a second number of transitions during a second time interval; (3) sensing the number of logic-0s and logic-1s occurring in the first and second time intervals; and (4) computing the value based at least in part on the number of logic-0s and logic-1s occurring in the first and second time intervals. During a compensation phase, inter-symbol interference may be compensated based on the value obtained in the sensing phase.

Circuits and methods for inter-symbol interference compensation are described. These circuits and methods may be used in connection with delta-sigma analog-to-digital converter. During a sensing phase, a value indicative of the inter-symbol interference may be sensed. The value may be obtained by (1) causing the ADC to generate a first number of transitions during a first time interval; (2) causing the ADC to generate a second number of transitions during a second time interval; (3) sensing the number of logic-0s and logic-1s occurring in the first and second time intervals; and (4) computing the value based at least in part on the number of logic-0s and logic-1s occurring in the first and second time intervals. During a compensation phase, inter-symbol interference may be compensated based on the value obtained in the sensing phase.