A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer, a dynamic element matching circuit and a digital to analog converter. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter is arranged for receiving the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a digital output signal according to the filtered summation signal. The dynamic element matching circuit is arranged for receiving the digital output signal to generate a shaped digital output signal for shaping element mismatch. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the shaped digital output signal to generate the feedback signal to the receiving circuit, wherein clock signals used by the quantizer and the dynamic element matching circuit have different frequencies.

Provided, among other things, is an apparatus for digitally processing a discrete-time signal that includes: an input line for accepting an input signal, processing branches coupled to the input line, and an adder coupled to outputs of the processing branches. First and second lowpass filters, each having a frequency response with a magnitude that varies approximately with frequency according to a product of raised functions, are included within baseband processors in such processing branches.

A hybrid digital-to-analog converter including a charge-sharing digital-to-analog converter and a charge redistribution digital-to-analog converter is provided. The charge-sharing digital-to-analog converter is configured to receive a digital input signal having multiple bits. The bits include a most-significant-bit and a least-significant-bit. The charge-sharing digital-to-analog converter is configured to convert the most-significant-bit to provide a first portion of an analog signal and selectively share charges of first capacitors during a successive approximation of the most-significant-bit. The charge redistribution digital-to-analog converter is configured to convert the least-significant-bit to provide a second portion of the analog signal. The charge redistribution digital-to-analog converter performs charge redistribution by selectively connecting second capacitors to receive reference voltages during a successive approximation of the least-significant-bit.

A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer with a negative capacitor circuit and a feedback circuit. The receiving circuit is arranged for receiving an input signal and a feedback signal to generate a first signal. The loop filter is coupled to the receiving circuit, and is arranged for receiving the first signal to generate a filtered signal. The quantizer is coupled to the loop filter, and is arranged for generating a digital output signal according to the filtered signal, wherein the negative capacitor circuit is arranged at an input terminal of the quantizer. The feedback circuit is arranged for receiving the digital output signal to generate the feedback signal.

An integrated circuit having power supply circuitry configured to generate a temperature dependent power supply voltage is provided. The power supply circuitry may include temperature sensors formed at different regions on the integrated circuit. The power supply circuitry may use a selected one of the temperature sensors to vary the temperature dependent power supply voltage. The power supply circuitry may include voltage clamping circuitry configured to clip the power supply voltage to an upper fixed voltage level when the power supply voltage exceeds a first predetermined threshold and to clip the power supply voltage to a lower fixed voltage level when the power supply voltage falls below a second predetermined threshold. The power supply circuitry may also include voltage overshoot-undershoot protection circuitry configured to keep the temperature dependent power supply voltage within a specified voltage range in the presence of transient perturbations in the temperature dependent power supply voltage.

A circuit, system, and method for measuring capacitance are described. A current may be received at an input of a conversion circuit. The current may be converted to a voltage signal which may be used to create a negative feedback current to the input of the conversion circuit and which may be demodulated digitally to provide a static digital output representative of a capacitance.

Provided, among other things, is an apparatus for digitally processing a discrete-time signal that includes: an input line for accepting an input signal, processing branches coupled to the input line, and an adder coupled to outputs of the processing branches. First and second lowpass filters, each having a frequency response with a magnitude that varies approximately with frequency according to a product of raised functions, are included within baseband processors in such processing branches.

A delta-sigma modulator includes a receiving circuit, a loop filter, a quantizer, a dynamic element matching circuit and a digital to analog converter. The receiving circuit is arranged for receiving a feedback signal and an input signal to generate a summation signal. The loop filter is arranged for receiving the summation signal to generate a filtered summation signal. The quantizer is arranged for generating a digital output signal according to the filtered summation signal. The dynamic element matching circuit is arranged for receiving the digital output signal to generate a shaped digital output signal for shaping element mismatch. The digital to analog converter is arranged for performing a digital to analog converting operation upon a signal derived from the shaped digital output signal to generate the feedback signal to the receiving circuit, wherein clock signals used by the quantizer and the dynamic element matching circuit have different frequencies.

A device may include an input terminal configured to receive an analog input signal. A device may include an output terminal configured to output a digital signal x, wherein the digital signal x includes a digital approximation of the analog input signal. A device may include an error correction system connected to the ADC, the error correction system including a first input terminal configured to receive an Nth powered version of the digital signal x, wherein N is a whole number equal to or greater than two, wherein the error correction system is configured to: use the Nth powered version of the digital signal x to determine a correction value; and modify the digital signal x to generate a corrected digital signal by applying the correction value to compensate for analog-to-digital conversion errors occurring within the ADC.

For continuous-time multi-stage noise shaping analog to digital converters (CT MASH ADCs), quantization noise cancellation often requires estimation of transfer functions, e.g., a noise transfer function of the front end modulator. To estimate the noise transfer function, a dither signal can be injected in the front end modulator. However, it is not trivial how the dither signal can be injected, since the dither signal can potentially leak to the back end modulator and cause overall noise degradation. To address some of these issues, the dither signal is injected post the flash analog to digital converter (ADC) of the front end modulator. Furthermore, dummy comparator structures can be used to synchronize the dither with the quantization noise of the targeted flash ADC.