A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.

A correction method and a correction circuit for a sigma-delta modulator (SDM) are provided. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC). The correction method includes the following steps: controlling the DAC not to receive the output of the quantizer; controlling the SDM to stop receiving signals; inputting a test signal to the DAC; converting the output of the loop filter to a digital signal; comparing the digital signal with a preset value; and adjusting the loop filter according to the result of comparing the digital signal and the preset value.

A correction method and a correction circuit for a sigma-delta modulator (SDM) are disclosed. The SDM includes a loop filter, a quantizer, and a digital-to-analog converter (DAC), and the loop filter includes a resonator. The correction circuit includes a memory and a control circuit. The memory stores multiple program instructions. The control circuit executes the program instructions to correct the SDM. The correction procedure of the SDM includes the following steps: inputting a test signal to the SDM; obtaining a signal characteristic value of an output signal of the SDM; and adjusting the resonator according to the signal characteristic value.

An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

A physical quantity sensor module includes: a resonant frequency shift based physical quantity sensor whose frequency adjusts with a adjust in physical quantity; a reference signal oscillator which outputs a reference signal; a frequency delta-sigma modulator which performs frequency delta-sigma modulation of the reference signal, using an operation signal based on a measurement target signal as an output from the resonant frequency shift based physical quantity sensor, and generates a frequency delta-sigma modulated signal; a first low-pass filter provided on an output side of the frequency delta-sigma modulator and operating synchronously with the measurement target signal as the output from the resonant frequency shift based physical quantity sensor; and a second low-pass filter provided on an output side of the first low-pass filter and operating synchronously with the reference signal.

A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.

A vibration rectification error correction device includes a first filter that operates in synchronization with the measured signal, and a second filter that operates in synchronization with the reference signal, in which the first filter generates a third signal based on a first signal having a first group delay amount and a second signal having a second group delay amount, the second filter receives a signal based on the third signal and outputs a fourth signal, and a first vibration rectification error and a second vibration rectification error have different polarities.

A failure determination circuit includes a first A/D conversion circuit that continuously A/D converts a first analog signal based on a first physical quantity measurement signal, a switching circuit that receives a plurality of signals including a second analog signal based on the first physical quantity measurement signal and a first reference voltage and outputs the plurality of signals in a time division manner, a second A/D conversion circuit that A/D converts the output of the switching circuit, and a determination circuit, and the determination circuit determines a failure of the first A/D conversion circuit using a signal based on a first digital signal obtained by A/D converting the first analog signal by the first A/D conversion circuit and a signal based on a second digital signal obtained by A/D converting the second analog signal by the second A/D conversion circuit.

A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.

An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multibit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.