An analog circuit including a voltage regulator, at least one analog-to-digital convertor (ADC), at least one comparator and a multiplexer is provided. The voltage regulator generates an output voltage. The at least one ADC generates at least one digital signal. The multiplexer is configured to conduct the at least one comparator to either the voltage regulator or the at least one ADC. When the voltage regulator is triggered, the multiplexer conducts the at least one comparator to the voltage regulator, and the voltage regulator generates the output voltage according to an output of the at least one comparator. When the at least one ADC is triggered, the multiplexer conducts the at least one comparator to the at least one ADC, and the at least one ADC generates the at least one digital signal according to the output of the at least one comparator.

Systems and methods for correction of sigma-delta analog-to-digital converters (ADCs) using neural networks are described. In an illustrative, non-limiting embodiment, a device may include: an ADC; a filter coupled to the ADC, where the filter is configured to receive an output from the ADC and to produce a filtered output; and a neural network coupled to the filter, where the neural network is configured to receive the filtered output and to produce a corrected output.

An apparatus includes a global baseliner circuit coupled with sensing channels of a sensing device. The global baseliner circuit has a signal generator to generate a rectified sinusoidal signal and a square wave having a frequency matching that of an excitation sinusoidal signal, and is to use the square wave to modulate the excitation sinusoidal signal provided at an output of the global baseliner circuit. A channel baseliner circuit is coupled between the global baseliner circuit and a sensing channel and that includes a switched capacitor coupled between the output of the global baseliner circuit and the sensing channel; a sigma-delta modulator coupled with the signal generator and to generate, from the rectified sinusoidal signal, a density-modulated bit stream; and a pair of AND gates to use the density-modulated bit stream and non-overlapping clock signals to generate outputs including density-modulated clock signals sent to switches of the switched capacitor.

A sigma delta modulator device includes a sampling circuit, a digital to analog converter circuit, an integrator circuit, and an analog to digital converter circuit. The sampling circuit is configured to sample an input signal, in order to generate a first signal. The digital to analog converter circuit is configured to convert a first digital signal to be a combination of a first reference voltage and a common mode voltage, in order to generate a second signal, in which the first reference voltage is one of a positive reference voltage and a negative reference voltage. The integrator circuit is configured to perform integration according to the first signal and the second signal, in order to generate a third signal. The analog to digital converter circuit is configured to quantize the third signal to generate an output signal, and to generate the first digital signal according to the output signal.

A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.

A DC/DC converter may be formed out of the combination of a first converter that is optimized to transfer energy from a voltage source to a load, and a second converter that receives a control signal derived from the load voltage to regulate the load voltage. The DC/DC converter may be configured as a sigma converter, a delta converter, or a sigma-delta converter. The mode of operation being selected according to the source voltage or the load voltage, either of which may vary over a wide range.

Systems and methods for improving the efficiency of a rotational dynamic element matching (DEM) for Delta Sigma converters. In some implementations, the systems and methods are provided for reducing intersymbol interference (ISI) of a Delta Sigma converter. A delta sigma converter architecture can include multiple I-DACs, and the output from each I-DAC can vary from the other l-DACs. Techniques include decreasing mismatch among multiple l-DACs while improving efficiency of rotational dynamic element matching.

A system and method of replicating and cancelling chopping folding error in delta-sigma modulators. The modulator may include a loop filter coupled to a quantizer providing a digital signal, chopper circuitry that chops analog signals of the loop filter at a chopping frequency, and chopping folding error cancellation circuitry that replicates and cancels a chopping folding error of the chopper circuitry to provide a corrected digital signal. A digital chopper or multiplier chops the digital signal to provide a chopped digital signal, and the chopped digital signal is either amplified or multiplied by a gain value or digitally filtered to replicate the chopping folding error, which is then subtracted from the digital signal for correction. The timing and duty cycle of the chopping frequency may be adjusted. Timing and duty cycle adjustment may be calibrated along with the filtering.

A sigma delta modulator device includes a sampling circuit, a digital to analog converter circuit, an integrator circuit, and an analog to digital converter circuit. The sampling circuit is configured to sample an input signal, in order to generate a first signal. The digital to analog converter circuit is configured to convert a first digital signal to be a combination of a first reference voltage and a common mode voltage, in order to generate a second signal, in which the first reference voltage is one of a positive reference voltage and a negative reference voltage. The integrator circuit is configured to perform integration according to the first signal and the second signal, in order to generate a third signal. The analog to digital converter circuit is configured to quantize the third signal to generate an output signal, and to generate the first digital signal according to the output signal.

Disclosed are a system and a battery management integration circuit using an incremental analog-to-digital converter (ADC), which can reduce the consumption of the amount of a bias current. The system includes an incremental ADC configured to perform accumulation on an analog signal during an oversampling period and a bias current generator configured to provide a bias current for the accumulation of the incremental ADC. The bias current generator provides a first amount of the bias current in a first period defined from start timing of oversampling to preset timing during the oversampling period, and provides a second amount of the bias current, smaller than the first amount of the bias current, in a second period subsequent to the first period.