A hardware module comprising circuitry configured to: store a sequence of n bits in a register of the hardware module; generate a signed integer comprising a magnitude component and a sign bit by: if the most significant bit of the sequence of n bits is equal to one: set each of the n−1 of the most significant bits of the magnitude component to be equal to the corresponding bit of the n−1 least significant bits of the sequence of n bits; and set the sign bit to be zero; if the most significant bit of the sequence of n bits is equal to zero: set each of the n−1 of the most significant bits of the magnitude component to be equal to the inverse of the corresponding bit of the n−1 least significant bits of the sequence of n bits; and set the sign bit to be one.

Encoding PAM4 or PAM8 symbols to have a power spectral density (PSD) similar to the PSD of a standard 8b10b Non-Return-to-Zero stream. In one embodiment, a transmitter includes first and second 8b10b encoders that receive first and second streams split from an original byte stream. The first and second 8b10b encoders output first and second 8b10b streams, respectively. The first and second 8b10b streams are fed into a 2-bit combiner that performs a linear combination of the first and second 8b10b streams. And a 4-level Pulse Amplitude Modulation encoder (PAM4 encoder) converts the linear combination of each two bits, received from the combiner, into a PAM4 symbol. Wherein the resulting stream of PAM4 symbols has PSD similar to the PSD of the standard 8b10b non-return-to-zero stream.

An encode apparatus and an encode method may be provided. The encoding apparatus may comprise a first stage and a second stage. The first stage may be configured to receive a first input, decode the first input, and produce a first output comprising the decoded first input. The second stage may be configured to receive a second input, receive the first output from the first stage, and convert the first input and the second input from a first coding system to a second coding system based on the second input and the first output. The second stage may produce a second output comprising the converted first input and the converted second input.

The least-significant-bits (LSBs) of a first data word of a first subset of a first plurality of data words may be compared to the LSBs of each data word of a second subset of a second plurality of data words. The first data word may then be mapped to a second data word of the second subset. A number of LSBs of the second data word matching LSBs of the first data word may be greater than a respective number of LSBs of each data word of a third subset of the second subset matching the LSBs of the first data word, where the third subset excludes the second data word and a most-significant-bit (MSB) of the second data word may be the same as a MSB of the first data word.

The least-significant-bits (LSBs) of a first data word of a first subset of a first plurality of data words may be compared to the LSBs of each data word of a second subset of a second plurality of data words. The first data word may then be mapped to a second data word of the second subset. A number of LSBs of the second data word matching LSBs of the first data word may be greater than a respective number of LSBs of each data word of a third subset of the second subset matching the LSBs of the first data word, where the third subset excludes the second data word and a most-significant-bit (MSB) of the second data word may be the same as a MSB of the first data word.

A hardware module comprising circuity configured to: store a sequence of n bits in a register of the hardware module; generate a signed integer comprising a magnitude component and a sign bit by: if the most significant bit of the sequence of n bits is equal to one: set each of the n1 of the most significant bits of the magnitude component to be equal to the corresponding bit of the n1 least significant bits of the sequence of n bits; and set the sign bit to be zero; if the most significant bit of the sequence of n bits is equal to zero: set each of the n1 of the most significant bits of the magnitude component to be equal to the inverse of the corresponding bit of the n1 least significant bits of the sequence of n bits; and set the sign bit to be one.

A hardware module comprising circuity configured to: store a sequence of n bits in a register of the hardware module; generate a signed integer comprising a magnitude component and a sign bit by: if the most significant bit of the sequence of n bits is equal to one: set each of the n1 of the most significant bits of the magnitude component to be equal to the corresponding bit of the n1 least significant bits of the sequence of n bits; and set the sign bit to be zero; if the most significant bit of the sequence of n bits is equal to zero: set each of the n1 of the most significant bits of the magnitude component to be equal to the inverse of the corresponding bit of the n1 least significant bits of the sequence of n bits; and set the sign bit to be one.

The present disclosure relates to partially written superblock treatment. An example apparatus includes a memory device operable as a multiplane memory resource including blocks organized as superblocks. The memory device is configured to maintain, internal to the memory device, included in a status of an open superblock, a page indicator corresponding to a last written page of the open superblock. The memory device is further configured, responsive to receipt, from a controller, of a read request to a page of the open superblock, determine from page map information maintained internal to the memory device and from the indicator of the last written page, which of a number of different read trim sets to use to read the page of the open superblock corresponding to the read request.

Encoding PAM4 or PAM8 symbols to have a power spectral density (PSD) similar to the PSD of a standard 8b10b Non-Return-to-Zero stream. In one embodiment, a transmitter includes first and second 8b10b encoders that receive first and second streams split from an original byte stream. The first and second 8b10b encoders output first and second 8b10b streams, respectively. The first and second 8b10b streams are fed into a 2-bit combiner that performs a linear combination of the first and second 8b10b streams. And a 4-level Pulse Amplitude Modulation encoder (PAM4 encoder) converts the linear combination of each two bits, received from the combiner, into a PAM4 symbol. Wherein the resulting stream of PAM4 symbols has PSD similar to the PSD of the standard 8b10b non-return-to-zero stream.

A pulse density modulation method includes the following steps: S01, obtaining a number of bits n of a binary density value d, setting a number of bits of a counter as n, an initial value of the counter is 0 or 1; S02, searching for a rightmost 1: obtaining a number of bits j of the rightmost 1 of a current value i of the counter counted from right to left; a number in the counter is a binary number; a minimum value of j is 1; S03, determining whether corresponding bits are equal; S04, adding the value i of the counter by 1, proceeding to a next period, and turning to the step S02.