A pulse density modulation method includes the following steps: S01, obtaining a number of bits n of a binary density value d, setting a number of bits of a counter as n, an initial value of the counter is 0 or 1; S02, searching for a rightmost 1: obtaining a number of bits j of the rightmost 1 of a current value i of the counter counted from right to left; a number in the counter is a binary number; a minimum value of j is 1; S03, determining whether corresponding bits are equal; S04, adding the value i of the counter by 1, proceeding to a next period, and turning to the step S02.

A pulse density modulation method includes the following steps: S01, obtaining a number of bits n of a binary density value d, setting a number of bits of a counter as n, an initial value of the counter is 0 or 1; S02, searching for a rightmost 1: obtaining a number of bits j of the rightmost 1 of a current value i of the counter counted from right to left; a number in the counter is a binary number; a minimum value of j is 1; S03, determining whether corresponding bits are equal; S04, adding the value i of the counter by 1, proceeding to a next period, and turning to the step S02.

A pulse density modulation method includes the following steps: S01, obtaining a number of bits n of a binary density value d, setting a number of bits of a counter as n, an initial value of the counter is 0 or 1; S02, searching for a rightmost 1: obtaining a number of bits j of the rightmost 1 of a current value i of the counter counted from right to left; a number in the counter is a binary number; a minimum value of j is 1; S03, determining whether corresponding bits are equal; S04, adding the value i of the counter by 1, proceeding to a next period, and turning to the step S02.

A parallel-to-serial conversion circuit may include first to fourth data lines; first to fourth parallel-to-serial converters configured to parallel-to-serial convert data of corresponding two data lines, among the first to fourth data lines, at a ratio of 2:1, respectively; and first to fourth drivers configured to transmit converted data of corresponding parallel-to-serial converter, among the first to fourth parallel-to-serial converters, respectively, to an output line, wherein two of the first to fourth drivers are simultaneously activated.

A parallel-to-serial conversion circuit may include first to fourth data lines; first to fourth parallel-to-serial converters configured to parallel-to-serial convert data of corresponding two data lines, among the first to fourth data lines, at a ratio of 2:1, respectively; and first to fourth drivers configured to transmit converted data of corresponding parallel-to-serial converter, among the first to fourth parallel-to-serial converters, respectively, to an output line, wherein two of the first to fourth drivers are simultaneously activated.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for encoding binary data are provided. One of the methods includes: obtaining a multimedia file from a storage device, extracting multiple bytes of binary data from the multimedia file, converting the binary data into 7-bit encoded data using an encoding algorithm, and sending one or more signals comprising the 7-bit encoded data to a remote computing device. The converting includes identifying multiple bits of data, each corresponding to a predetermined bit position of one of the bytes of binary data, generating one or more bytes of combined-bit data by combining the identified bits of data, generating one or more bytes of remaining-bit data, and generating the 7-bit encoded data by concatenating the one or more bytes of combined-bit data and the one or more bytes of remaining-bit data.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for encoding binary data are provided. One of the methods includes: obtaining a multimedia file from a storage device, extracting multiple bytes of binary data from the multimedia file, converting the binary data into 7-bit encoded data using an encoding algorithm, and sending one or more signals comprising the 7-bit encoded data to a remote computing device. The converting includes identifying multiple bits of data, each corresponding to a predetermined bit position of one of the bytes of binary data, generating one or more bytes of combined-bit data by combining the identified bits of data, generating one or more bytes of remaining-bit data, and generating the 7-bit encoded data by concatenating the one or more bytes of combined-bit data and the one or more bytes of remaining-bit data.

A method, system, and device are directed to audio input bit-size conversion for compatibility to audio processing systems with an expected input sample bit-size.

A method of data compression performed by at least one core communicating with a central memory. The input data presents a two-dimensional input array formed by a plurality data items stored contiguously in the central memory according to a contiguous direction. The method comprises a step of wavelet transform comprising the following sub-steps: forming from the input array at least one tile comprising a plurality of consecutive data block columns, each data block column being formed by a plurality of lines of consecutive data items according to the contiguous direction, the length of each line being a multiple of the cache line length; and for each data block column computing dot products between a filter vector and each group of N lines using fused multiply-add instructions for the core.

A parallel-to-serial conversion circuit may include first to fourth data lines; first to fourth parallel-to-serial converters configured to parallel-to-serial convert data of corresponding two data lines, among the first to fourth data lines, at a ratio of 2:1, respectively; and first to fourth drivers configured to transmit converted data of corresponding parallel-to-serial converter, among the first to fourth parallel-to-serial converters, respectively, to an output line, wherein two of the first to fourth drivers are simultaneously activated.