Patent classifications
H03M7/06
SYSTEMS AND METHODS FOR VARIABLE-LENGTH ENCODING AND DECODING FOR ENHANCING COMPUTER SYSTEMS
A method for variable length decoding, the method including: receiving, in a default word length mode, at least one first data word having a default first word length; combining the received at least one first data word as a first portion of data; receiving, after the at least one first data word, a transition word indicative of transitioning to a variable word length mode; receiving, after the transition word, a first word length word indicative of a second word length; receiving, after the first word length word, at least one second data word having the second word length; and combining the received at least one second data word as a second portion of the data.
Method and apparatus for converting from floating point to integer representation
Apparatus and methods for conversion from floating point to signed integer representation are provided. Two's complementation and determination of a shift control signal indicating the number of bit positions for shifting the two's complemented mantissa to produce the signed integer are performed in parallel. Generation of the shift control signal, including application of an optional scaling factor, is performed using an adder, with the most significant bit of input floating point exponent inverted and an external carry-in of one. Two's complementation for generation of the signed integer from the mantissa is performed using an adder. Certain aspects may be utilized for purposes other than format conversion. The two's complementation may be used for general conversion from unsigned to signed integer format or from signed to unsigned integer format.
Method and apparatus for converting from floating point to integer representation
Apparatus and methods for conversion from floating point to signed integer representation are provided. Two's complementation and determination of a shift control signal indicating the number of bit positions for shifting the two's complemented mantissa to produce the signed integer are performed in parallel. Generation of the shift control signal, including application of an optional scaling factor, is performed using an adder, with the most significant bit of input floating point exponent inverted and an external carry-in of one. Two's complementation for generation of the signed integer from the mantissa is performed using an adder. Certain aspects may be utilized for purposes other than format conversion. The two's complementation may be used for general conversion from unsigned to signed integer format or from signed to unsigned integer format.