Embodiments of the invention are directed to a computer-implemented method of for parallel conversion to binary coded decimal format. The method includes receiving, by a floating point unit (FPU), a value in binary floating point (BFP) format. The BFP value includes an integer part and a fractional part. The FPU converts the BFP value to a binary coded decimal (BCD) value. In parallel to converting the BFP value to a BCD value, the FPU performs a rounding operation on the BFP value. The FPU receives the rounding information and operates on the BCD value accordingly.

A method and information handling system (IHS) converts a globally unique identifier to an electronic data interchange document identifier. The method includes receiving a globally unique identifier and converting the globally unique identifier into 128 binary bits. The 128 binary bits are selectively separated to form groups of bits that translate to integers. Each integer is replaced with an assigned alphanumeric character selected from an alphanumeric character map to form an encoded alphanumeric string of characters for use as an electronic data interchange document identifier.

A method and information handling system (IHS) converts a globally unique identifier to an electronic data interchange document identifier. The method includes receiving a globally unique identifier and converting the globally unique identifier into 128 binary bits. The 128 binary bits are selectively separated to form groups of bits that translate to integers. Each integer is replaced with an assigned alphanumeric character selected from an alphanumeric character map to form an encoded alphanumeric string of characters for use as an electronic data interchange document identifier.

A circuit includes an amplifier having an input and an output. A voltage comparator has an input and first and second outputs. The input of the voltage comparator is coupled to the output of the amplifier. A variable capacitor circuit is coupled between the input and the output of the amplifier and is coupled to the first output of the voltage comparator. A charge dump circuit has an input and an output. The input of the charge dump circuit is coupled to the second output of the voltage comparator. The output of the charge dump circuit is coupled to the input of the amplifier.

A circuit includes an amplifier having an input and an output. A voltage comparator has an input and first and second outputs. The input of the voltage comparator is coupled to the output of the amplifier. A variable capacitor circuit is coupled between the input and the output of the amplifier and is coupled to the first output of the voltage comparator. A charge dump circuit has an input and an output. The input of the charge dump circuit is coupled to the second output of the voltage comparator. The output of the charge dump circuit is coupled to the input of the amplifier.

A processing circuit configured to: receive original data; partition the original data into a plurality of original q-bit words; assemble a data packet including N original q-bit words from the plurality of original q-bit words; identify a first encoder value and a second encoder value that are absent from the values of the N original q-bit words; encode the N original q-bit words based on a one-to-one mapping from q-bit original values to q-bit encoded values based on the first encoder value and the second encoder value to generate N encoded q-bit payload words, the N encoded q-bit payload words being free of words that are all-zeroes and free of words that are all-ones; generate a key representing the first encoder value and the second encoder value; and transmit the key and the N encoded q-bit payload words.

A non-transitory computer-readable recording medium having stored therein a coding program that causes a computer to execute a process. The process includes coding a numerical value to be coded, into a numeric code of base-2.sup.n representation; and generating code data that have been added with an instantaneous code indicating the number of digits of the base-2.sup.n representation of the numerical value to be coded, wherein n is a natural number equal to or greater than 1.

A non-transitory computer-readable recording medium having stored therein a coding program that causes a computer to execute a process. The process includes coding a numerical value to be coded, into a numeric code of base-2.sup.n representation; and generating code data that have been added with an instantaneous code indicating the number of digits of the base-2.sup.n representation of the numerical value to be coded, wherein n is a natural number equal to or greater than 1.

A method of detecting starting positions, sizes, and number of records of fields within a bit stream, by formatting the bit stream into a frame using positive logic, then performing decimal conversion of different predetermined field lengths on the framed bit stream, to produce channels. Noise is either removed or amplified from the framed bit stream, and the frame and the channels are input to an image detection module to identify fields within the framed bit stream.

A method of detecting starting positions, sizes, and number of records of fields within a bit stream, by formatting the bit stream into a frame using positive logic, then performing decimal conversion of different predetermined field lengths on the framed bit stream, to produce channels. Noise is either removed or amplified from the framed bit stream, and the frame and the channels are input to an image detection module to identify fields within the framed bit stream.