A wireless signal digital conversion device according to an embodiment of the present disclosure comprises: a plurality of RF signal processing units for receiving wireless signals, and adjusting the voltage levels of the wireless signals on the basis of automatic gain values; a plurality of unit ADCs for receiving in-phase signals and quadrature phase signals of the RF signal processing units, and performing analog-to-digital conversion on the basis of different differential reference voltages; an encoder unit for generating binary data having less bits than binary data outputted from the unit ADCs on the basis of the binary data outputted from the unit ADCs; and an automatic gain control unit for generating automatic gain values on the basis of the output of a spatial ADC. A terminal of the present disclosure can be linked to an artificial intelligence module, a drone (unmanned aerial vehicle (UAV)), a robot, an augmented reality (AR) device, a virtual reality (VR) device, a device related to 6G services, and the like.

A wireless signal digital conversion device according to an embodiment of the present disclosure comprises: a plurality of RF signal processing units for receiving wireless signals, and adjusting the voltage levels of the wireless signals on the basis of automatic gain values; a plurality of unit ADCs for receiving in-phase signals and quadrature phase signals of the RF signal processing units, and performing analog-to-digital conversion on the basis of different differential reference voltages; an encoder unit for generating binary data having less bits than binary data outputted from the unit ADCs on the basis of the binary data outputted from the unit ADCs; and an automatic gain control unit for generating automatic gain values on the basis of the output of a spatial ADC. A terminal of the present disclosure can be linked to an artificial intelligence module, a drone (unmanned aerial vehicle (UAV)), a robot, an augmented reality (AR) device, a virtual reality (VR) device, a device related to 6G services, and the like.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

A quad signal generator circuit generates four 2.sup.N-1 bit control signals in response to a 2.sup.N-1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2.sup.N-1 unit DAC elements, with each unit DAC element including four switching circuits controlled by corresponding bits of the four 2.sup.N-1 bit control signals. Outputs of the 2.sup.N-1 unit DAC elements are summed to generate an analog output signal. The quad signal generator circuit controls a time delay applied to clock signals relative to the 2.sup.N-1 bit thermometer coded signal and a time delay applied to the 2.sup.N-1 bit thermometer coded signal relative to the delayed clock signals in logically generating the four 2.sup.N-1 bit control signals. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2.sup.N-1 bit thermometer coded signal.

Techniques for setting a gain of an amplifier circuit in which the external resistor of the amplifier circuit is used to determine an internal gain setting to select. A voltage across the external resistor can be compared to an on-chip reference, and then used to program the desired gain. The techniques can mitigate or eliminate the need for a high-accuracy external resistor and can allow substantial improvements in initial gain accuracy and gain drift for existing boards and/or systems with only a bill of material change.

A method for training an object detection system includes estimating a location of a first object in an environment based on a density cluster map generated from a plurality of images of the environment. The method also includes generating one or more negative training samples of the first object in the environment based on the plurality of images, each of the one or more negative training samples corresponding to a second object at a location in the environment that is different than the estimated location of the first object. The method further includes generating positive training samples from a set of images of the first object. The method also includes training the object detection system to detect the first object based on the positive training samples and the negative training sample.

A method for training an object detection system includes estimating a location of a first object in an environment based on a density cluster map generated from a plurality of images of the environment. The method also includes generating one or more negative training samples of the first object in the environment based on the plurality of images, each of the one or more negative training samples corresponding to a second object at a location in the environment that is different than the estimated location of the first object. The method further includes generating positive training samples from a set of images of the first object. The method also includes training the object detection system to detect the first object based on the positive training samples and the negative training sample.

A phase interpolator includes a decoder, a digital-to-analog converter (DAC), and a phase mixer. The decoder generates first and second thermometer codes and a selection signal based on a code. The DAC includes unit cells, determines two of weight signals as first and second target weight signals based on the selection signal, and adjusts a current of the first and second target weight signals by controlling the unit cells based on the first and second thermometer codes and the selection signal. The phase mixer determines two of input clock signals as first and second target clock signals and generates an output clock signal based on the first and second target weight signals and the first and second target clock signals. A phase of the output clock signal is between phases of the first and second target clock signals. The unit cells include different first and second unit cells.

A time to digital circuit may provide a time measurement of an event, or a time measurement of a duration between multiple events. Various electronic devices may include one or more time to digital circuits. A time to digital circuit may include circuitry to use Thermometer Code for measuring the duration of the time. For example, the time to digital circuit may generate alternating signals using a ring oscillator when receiving an indication of an event. Moreover, the time to digital circuit may convert the alternating signals to a consistent signal with only one transition between high and low signals in multiple consecutive signals. Furthermore, the time to digital circuit may correct erroneous signal values of the consistent signals when multiple transitions between high and low signals in multiple consecutive signals occurs.

A dynamic element method includes the following operations: summing up most significant bits of a digital code in a previous period and a pointer signal in the previous period, in order to generate a first signal; outputting the first signal to be an adjusted pointer signal according to a clock signal; and decoding the adjusted pointer signal to be control signals, in which the control signals are configured to set corresponding relations of components of a first digital to analog converter circuits and the most significant bits, in order to utilize the components to convert the most significant bits.