A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.

A readout circuit for use in an image sensor includes a plurality of comparators. Each one of the plurality of comparators is coupled to receive a ramp signal and a respective analog image data signal from a respective one of a plurality of column bit lines to generate a respective comparator output. Each one of a plurality of arithmetic logic units (ALUs) is coupled to receive phase-aligned Gray code (GC) outputs generated by a GC generator. Each one of the plurality of ALUs is further coupled to a respective one of the plurality of comparators to receive the respective comparator output. Each one of the plurality of ALUs is coupled to latch the phase-aligned GC outputs in response to the respective comparator output to generate a respective digital image data signal.

A quad signal generator circuit generates four 2.sup.N−1 bit control signals in response to a sampling clock and a 2.sup.N−1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2.sup.N−1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2.sup.N−1 bit control signals. Outputs of the 2.sup.N−1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2.sup.N−1 bit control signals such that all logic states of bits of the four 2.sup.N−1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2.sup.N−1 bit thermometer coded signal.

Disclosed are an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter. The analog-to-digital converter error shaping circuit includes a decentralized capacitor array, a data weighted average module, a mismatch error shaping module, a control logic generation circuit, a digital filter and a decimator. The decentralized capacitor array includes two symmetrically arranged capacitor array units, each capacitor array unit includes a first sub-capacitor array of a high segment bit and a second sub-capacitor array of a low segment bit. The data weighted average module is configured to eliminate correlation between the first sub-capacitor array and an input signal, and the mismatch error shaping module is configured to eliminate correlation between the second sub-capacitor array and the input signal.

To simplify the circuit configuration and design of an analog-digital converter. A low-order bit latch section latches, as low-order bits, Gray code data corresponding to a reference clock by using, as a trigger, inversion of an output of a comparator. A high-order bit counter section counts one or both of edges of a CNT signal corresponding to the reference clock and stops a count of high-order bits by using, as a trigger, inversion of an output of the comparator.

To simplify the circuit configuration and design of an analog-digital converter. A low-order bit latch section latches, as low-order bits, Gray code data corresponding to a reference clock by using, as a trigger, inversion of an output of a comparator. A high-order bit counter section counts one or both of edges of a CNT signal corresponding to the reference clock and stops a count of high-order bits by using, as a trigger, inversion of an output of the comparator.

A digital-to-analog converter for generating an analog output voltage in response to a digital value comprising a plurality of bits, the converter including: (i) a first switched resistor network having a first configuration and for converting a first input differential signal into a first analog output in response to a first set of bits in the plurality of bits; and (ii) a second switched resistor network, coupled to the first switched resistor network, having a second configuration, differing from the first configuration, and for converting a second input differential signal into a second analog output in response to a second set of bits in the plurality of bits.

Embodiments are disclosed for a lookup table-based coding mechanism for communication systems. An example method includes receiving a signal to be transmitted, converting the signal into a converted analog signal using a digital to analog converter, receiving channel state information for a channel, calibrating the lookup table based on the channel state information, utilizing the calibrated lookup table to generate a coded analog signal based on the converted signal, and transmitting the coded analog signal, wherein the coded signal compensates for channel distortion of the channel.

Embodiments are disclosed for a lookup table-based coding mechanism for communication systems. An example method includes receiving a signal to be transmitted, converting the signal into a converted analog signal using a digital to analog converter, receiving channel state information for a channel, calibrating the lookup table based on the channel state information, utilizing the calibrated lookup table to generate a coded analog signal based on the converted signal, and transmitting the coded analog signal, wherein the coded signal compensates for channel distortion of the channel.

A quad signal generator circuit generates four 2.sup.N−1 bit control signals in response to a sampling clock and a 2.sup.N−1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2.sup.N−1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2.sup.N−1 bit control signals. Outputs of the 2.sup.N−1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2.sup.N−1 bit control signals such that all logic states of bits of the four 2.sup.N−1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2.sup.N−1 bit thermometer coded signal.