A cluster receives a request to store an object using replication or erasure coding. The cluster writes the object using erasure coding. A manifest is written that includes an indication of erasure coding and a unique identifier for each segment. The cluster returns a unique identifier of the manifest. The cluster receives a request from a client that includes a unique identifier. The cluster determines whether the object has been stored using replication or erasure coding. If using erasure coding, the method reads a manifest. The method identifies segments within the cluster using unique segment identifiers of the manifest. Using these unique segment identifiers, the method reconstructs the object. A persistent storage area of another disk is scanned to find a unique identifier of a failed disk. If using erasure coding, a missing segment previously stored on the disk is identified. The method locates other segments. Missing segments are regenerated.

A cluster receives a request to store an object using replication or erasure coding. The cluster writes the object using erasure coding. A manifest is written that includes an indication of erasure coding and a unique identifier for each segment. The cluster returns a unique identifier of the manifest. The cluster receives a request from a client that includes a unique identifier. The cluster determines whether the object has been stored using replication or erasure coding. If using erasure coding, the method reads a manifest. The method identifies segments within the cluster using unique segment identifiers of the manifest. Using these unique segment identifiers, the method reconstructs the object. A persistent storage area of another disk is scanned to find a unique identifier of a failed disk. If using erasure coding, a missing segment previously stored on the disk is identified. The method locates other segments. Missing segments are regenerated.

A semiconductor system includes a controller configured to, in a write operation, output write data and a write error code through at least any one of input/output lines, and in a read operation, receive read data and a read error code through at least any one of the input/output lines and detect a failure of the input/output lines depending on whether the read data is error-corrected; and a semiconductor device configured to, in the write operation, correct an error of the write data based on the write error code, store the error-corrected write data and store the write error code, and in the read operation, correct an error of the write data based on the write error code stored in the write operation, output the error-corrected write data as the read data, and output the write error code stored in the write operation, as the read error code.

An apparatus and method are provided for generating an error code for a block comprising a plurality of data bits and a plurality of address bits. The apparatus has block generation circuitry to generate a block comprising a plurality of data bits and a plurality of address bits, and error code generation circuitry for receiving that block and a mask array comprising a plurality of mask rows, and for then applying an error code generation algorithm to generate an error code for the block. The error code comprises a plurality of check bits, where each check bit is determined using the block and a corresponding mask row of the mask array. Each mask row comprises a plurality of mask bits, each mask bit being associated with a corresponding bit of the block. At least one mask row has its mask bit values constrained so as to ensure that when all of the data bits of the block have the same value, the error code generated by the error code generation circuitry has at least one check bit having a different value to the value of the data bits irrespective of the value of the address bits. In addition to supporting detection and/or correction of errors in the data bits, such an approach also allows memory address decode errors to be detected whilst in addition allowing detection of stuck at zero or stuck at one errors in a memory's output.

An apparatus and method are provided for generating an error code for a block comprising a plurality of data bits and a plurality of address bits. The apparatus has block generation circuitry to generate a block comprising a plurality of data bits and a plurality of address bits, and error code generation circuitry for receiving that block and a mask array comprising a plurality of mask rows, and for then applying an error code generation algorithm to generate an error code for the block. The error code comprises a plurality of check bits, where each check bit is determined using the block and a corresponding mask row of the mask array. Each mask row comprises a plurality of mask bits, each mask bit being associated with a corresponding bit of the block. At least one mask row has its mask bit values constrained so as to ensure that when all of the data bits of the block have the same value, the error code generated by the error code generation circuitry has at least one check bit having a different value to the value of the data bits irrespective of the value of the address bits. In addition to supporting detection and/or correction of errors in the data bits, such an approach also allows memory address decode errors to be detected whilst in addition allowing detection of stuck at zero or stuck at one errors in a memory's output.

An encoder receives a concatenated encoder input block d, splits d into an outer code input array a, and encodes a using outer codes to generate an outer code output array b. The encoder generates, from b, a concatenated code output array x using a layered polarization adjusted convolutional (LPAC) code. A decoder counts layers and carries out an inner decoding operation for a layered polarization adjusted convolutional (LPAC) code to generate an inner decoder decision {tilde over (b)}.sub.i from a concatenated decoder input array y and a cumulative decision feedback ({circumflex over (b)}.sub.1, {circumflex over (b)}.sub.2, . . . , {circumflex over (b)}.sub.i−1). The decoder carries out an outer decoding operation to generate from {tilde over (b)}.sub.i an outer decoder decision â.sub.i, and carries out a reencoding operation to generate a decision feedback {circumflex over (b)}.sub.i from â.sub.i, where the number of layers is an integer greater than one, with a concatenated decoder output block {circumflex over (d)} being generated from outer decoder decisions.

An encoder receives a concatenated encoder input block d, splits d into an outer code input array a, and encodes a using outer codes to generate an outer code output array b. The encoder generates, from b, a concatenated code output array x using a layered polarization adjusted convolutional (LPAC) code. A decoder counts layers and carries out an inner decoding operation for a layered polarization adjusted convolutional (LPAC) code to generate an inner decoder decision {tilde over (b)}.sub.i from a concatenated decoder input array y and a cumulative decision feedback ({circumflex over (b)}.sub.1, {circumflex over (b)}.sub.2, . . . , {circumflex over (b)}.sub.i−1). The decoder carries out an outer decoding operation to generate from {tilde over (b)}.sub.i an outer decoder decision â.sub.i, and carries out a reencoding operation to generate a decision feedback {circumflex over (b)}.sub.i from â.sub.i, where the number of layers is an integer greater than one, with a concatenated decoder output block {circumflex over (d)} being generated from outer decoder decisions.

This document discloses techniques, apparatuses, and systems for sparse encodings for control signals. Integrated circuits (ICs) may transmit various signals to manage interactions between circuit components of the IC. These critical signals are common targets for malicious attacks because, when altered, they can cause the IC to perform differently than is intended, and in some cases, bypass security measures. To protect against these attacks, the sparse encodings for control signals described herein transmit critical signals with sparse encodings. Further, multiple rails may be used to transmit a single bit of the sparsely encoded critical signals across each rail. In this way, the techniques described herein may provide a scalable solution that may be adjusted differently based on each implementation.

Various implementations described herein are directed to a memory device. The memory device may include a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device may include a second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code. The second interleaving circuit may interleave data bits from multiple different data words and store modified data words based on the multiple different data words.

A method for data communication between a first node and a second node over a data path includes determining one or more redundancy messages from data messages at the first node using an error correcting code and transmitting messages from the first node to the second node. The transmitted messages include the data messages and the redundancy messages. The method includes, receiving, at the first node, a first plurality of messages including messages indicative of a rate of arrival at the second node of the messages transmitted from the first node and messages indicative of successful and unsuccessful delivery of the messages transmitted from the first node to the second node. A first transmission limit and a second transmission limit are maintained according to the first plurality of messages. Transmission of messages from the first node to the second node is limited according to the maintained first transmission limit, and according to the second transmission limit.