A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups, and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups so that the puncturer selects parity bits included in the some of the bit groups positioned at the predetermined positions sequentially and selects parity bits included in the remainder of the bit groups without an order.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups, and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups so that the puncturer selects parity bits included in the some of the bit groups positioned at the predetermined positions sequentially and selects parity bits included in the remainder of the bit groups without an order.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups, and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups so that the puncturer selects parity bits included in the some of the bit groups positioned at the predetermined positions sequentially and selects parity bits included in the remainder of the bit groups without an order.

A receiver includes a polar decoder for decoding an encoded codeword transmitted over a communication channel. The receiver includes a front end to receive over a communication channel a codeword including a sequence of bits modified with noise of the communication channel and a soft decoder operated by a processor to produce a soft output of the decoding. The codeword is encoded by at least one polar encoder with a polar code. The processor is configured to estimate possible values of the bits of the received codeword using a successive cancelation list (SCL) decoding to produce a set of candidate codewords, determine a distance between each candidate codeword and a soft input to the soft decoder, and determine a likelihood of a value of a bit in the sequence of bits using a difference of distances of the candidate codewords closest to the received codeword and having opposite values at the position of the bit.

A transmitter for transmitting an encoded codeword over a communication channel is described. The transmitter includes a source to accept source data, an irregular polar encoder operated by a processor to encode the source data with at least one polar code to produce an encoded codeword, a modulator to modulate the encoded codeword, and a front end to transmit the modulated and encoded codeword over the communication channel, wherein the polar code is specified by a set of regular parameters and a set of irregular parameters.

A transmitter for transmitting an encoded codeword over a communication channel includes a source to accept source data, an irregular polar encoder operated by a processor to encode the source data with at least one polar code to produce the encoded codeword, a modulator to modulate the encoded codeword, and a front end to transmit the modulated and encoded codeword over the communication channel. The polar code is specified by a set of regular parameters including one or combination of parameters defining a number of data bits in the codeword, a parameter defining a data index set specifying locations of frozen bits in the encoded codeword, and a parameter defining a number of parity bits in the encoded codeword. The polar code is further specified by a set of irregular parameters including one or combination of parameters defining an irregularity of values of at least one regular parameter of the polar code, a parameter defining an irregularity of permutation of the encoded bits, a parameter defining an irregularity of polarization kernels in the polar code, and a parameter defining an irregularity in selection of de-activated exclusive-or operations on different stages of the polar encoding, and wherein the irregular polar encoder encodes the codeword using the regular and the irregular parameters of the polar code.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

The present patent application relates to a transmission method and corresponding receiving methods. The transmission method comprises: selecting K number of data streams for transmission, wherein each data stream comprises one or more data messages; and independently for each data stream k=0, . . . , K1: encoding and modulating data messages of the kth data stream using a Trellis Coded Modulation, TCM, scheme TCM.sub.k, interleaving the encoded and modulated data messages of the k-th data stream by using a stream specific interleaver .sub.k, scrambling the interleaved data messages of the k-th data stream by using a stream specific scrambling sequence; combining all scrambled data messages of the K number of data streams into at least one transmission signal s(l); and transmitting the at least one transmission signal s(l) over a radio channel of the wireless communication system.

Techniques are disclosed relating to circuitry configured to interleave data, e.g., for use to process error correcting codes for wireless data transmission. In some embodiments an apparatus includes one or more circuit elements configured to receive input data samples, a plurality of polynomial coefficients, a start index, and information indicating a window size for non-sequential traversal of interleaver indices. The polynomial coefficients may include coefficients for at least a third-order polynomial. In some embodiments, the one or more circuit elements are further configured to generate interleaved bank and address information for writing the input data samples to the plurality of memory blocks, based on an order of the polynomial, a code block length, the start index, and the information indicating the window size. In some embodiments, the apparatus also includes output circuitry configured to provide interleaved data samples from the memory blocks.