A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 64-symbol mapping.

An embodiment of the present disclosure contemplates a data sending and receiving method and apparatus. A first FEC unit of a sending device sends, by using a first channel, a first data stream on which first FEC encoding has been performed; a second FEC unit of the sending device sends, by using a second channel, a second data stream on which second FEC encoding has been performed; and the sending device performs interleaving on the first data stream and the second data stream, to obtain an output data stream, and sends the output data stream to a receiving device and error correction capability of a receiving device could be improved. In addition, in the present disclosure, an operation of writing by row and reading by column does not need to be performed. Therefore, no delay is generated.

According to some embodiments, a method of operation of a wireless transmitter in a wireless communication network comprises: encoding a set of information carrying data bits u of length K with a linear outer code to generate a set of outer parity bits p along with the data bits u; interleaving the set of outer parity bits p and the data bits u using a predetermined interleaving mapping function that depends on the number of data bits K and is operable to distribute some bits of the set of parity bits p in front of some data bits u; and encoding the interleaved bits using a Polar encoder to generate a set of encoded bits x. Various interleaving mapping functions are disclosed.

The present invention discloses a polar code encoding method and encoding apparatus. The method includes: mapping M reserved bits of a broadcast signaling respectively to M low-reliability information bits in K information bits of a polar code, and mapping remaining bits of the broadcast signaling to remaining information bits of the K information bits, to obtain bits after mapping, where M<K, and both M and K are positive integers; and performing polar code encoding on the bits after mapping, to obtain coded bits after encoding. Embodiments of the present invention can improve broadcast signaling transmission reliability.

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding of input bits based on a parity check matrix including information word bits and parity bits, the LDPC codeword including a plurality of bit groups each including a plurality of bits; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the interleaver is further configured to interleave the LDPC codeword such that a bit included in a predetermined bit group from among the plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

The present technology relates to a transmission method and a reception device for securing favorable communication quality in data transmission using an LDPC code. In group-wise interleaving, the LDPC code with a code length N of 69120 bits is interleaved in units of 360-bit bit groups 0 to 191. In group-wise deinterleaving, a sequence of the LDPC code after group-wise interleaving is returned to an original sequence. The present technology can be applied, for example, in a case of performing data transmission using an LDPC code, and the like.

A detection circuit performs a turbo detection process to recover a frame of data symbols from a received signal, the data symbols of the frame having been effected, during transmission, by a Markov process with the effect that the data symbols of the frame in the received signal are dependent one or more preceding data symbols which can be represented as a trellis having a plurality of trellis stages. The detection circuit comprises a plurality of processing elements, each of the processing elements is associated with one of the trellis stages representing the dependency of the data symbols of the frame according to the Markov process and each of the processing elements is configured to receive one or more soft decision values corresponding to one or more data symbols associated with the trellis stage, and each of one or more of the processing elements is configured, in one clock cycle to receive fixed point data representing a priori forward state metrics a priori backward state metrics, and fixed point data representing a priori soft decision values for the one or more data symbols being detected for the trellis stage. For each of a plurality of clock cycles of the turbo detection process, the detection circuit is configured to process, for each of the processing elements representing the trellis stages, the a priori information for the one or more data symbols being detected for the trellis stage associated with the processing element, and to provide the extrinsic soft decision values corresponding to the one or more data symbols for a next clock cycle of the turbo detection process.

[Object] To make it possible to transmit data more flexibly and with a lesser burden in an IDMA system. [Solution] There is provided an apparatus including: an acquisition unit configured to acquire an information block generated from transmission data for a user and subjected to error correction coding; and an interleaving unit configured to interleave a bit sequence of the information block using an interleaver unique to the user. The interleaving unit interleaves the bit sequence by interleaving each of two or more partial sequences obtained from the bit sequence.

A modulator and a modulation method using a non-uniform 16-symbol signal constellation are disclosed. The modulator includes a memory and a processor. The memory receives a codeword corresponding to a low-density parity check (LDPC) code having a code rate of 4/15. The processor maps the codeword to 16 symbols of the non-uniform 16-symbol signal constellation on a 4-bit basis.

An interleaving and mapping method and a deinterleaving and demapping method for an LDPC codeword are provided. The interleaving and mapping method comprises: performing first bit interleaving on a check part of the LDPC codeword to obtain a check bit stream; splicing an information bit part of the codeword and the check bit stream into a codeword after the first bit interleaving; dividing the codeword after the first bit interleaving into multiple consecutive bit subblocks in a predetermined length, and changing the order of the bit subblocks according to a corresponding permutation order (bit-swapping pattern) to form a codeword after second bit interleaving; dividing the codeword after the second bit interleaving into two parts, and writing the two parts into storage space in a column order respectively and reading the two parts from the storage space in a row order respectively to obtain a codeword after third bit interleaving; and performing constellation mapping on the codeword after the third bit interleaving according to a constellation diagram to obtain a symbol stream; the permutation orders (bit-swapping patterns) and the constellation diagrams used in the interleaving and mapping processing of LDPC codes with different code rates, code length and LDPC code tables are designed and optimized using theoretical analysis. The technical solution reduces the receiving threshold of the receiving end.