The present invention relates to a method of transmitting and a method of receiving signals an corresponding apparatus. One aspect of the present invention relates to an efficient L1 signaling method for an efficient transmitter and an efficient receiver using the efficient L1 signaling method for an efficient cable broadcasting.

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 7/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.

A transmitting apparatus is provided. The transmitting apparatus includes: an encoder configured to generate a low-density parity check (LDPC) codeword by LDPC encoding based on a parity check matrix; an interleaver configured to interleave the LDPC codeword; and a modulator configured to map the interleaved LDPC codeword onto a modulation symbol, wherein the modulator is further configured to map a bit included in a predetermined bit group from among a plurality of bit groups constituting the LDPC codeword onto a predetermined bit of the modulation symbol.

A transmission apparatus includes a signal processing circuit configured to obtain information data bits to be transmitted; add known information data bits to the information data bits to generate first data blocks; perform error-correction coding on the first data blocks to generate first coded data blocks including parity data blocks such that the first coded data blocks satisfy a first code rate; remove the known information data bits from the first coded data blocks to generate second coded data blocks, the second coded data blocks satisfying a second code rate different from the first code rate; and modulate the second coded data blocks using a modulation scheme to generate a modulated signal, which is then transmitted. A number of the known information data bits depends on a number of the information data bits such that the first code rate is fixed regardless of the number of the information data bits.

A data transmission method, apparatus, and system are applied to the field of communication technologies. The method includes: performing demultiplexing processing on obtained y first data streams to obtain x second data streams, where the y first data streams are obtained through bit multiplexing processing; mapping the x second data streams at a granularity of n bits to obtain z third data streams; and outputting the z third data streams over an output lane, where y, x, n, and z are all positive integers, and n≥2. The method may be applied to an Ethernet high-speed interface.

A parity interleaving apparatus and method for fixed length signaling information are disclosed. A parity interleaving apparatus according to an embodiment of the present invention includes a processor configured to generate a parity bit string for parity puncturing by segmenting parity bits of an LDPC codeword whose length is 16200 and whose code rate is 3/15, into a plurality of groups, and group-wise interleaving the groups using an order of group-wise interleaving; and memory configured to provide the parity bit string for parity puncturing to a parity puncturing unit.

A decoding circuit and a decoding method based on the Viterbi algorithm are provided. The decoding method includes the following steps: decoding an encoded data based on the Viterbi algorithm to generate a decoded data; performing error correction on the decoded data to obtain a data content of the encoded data; comparing the decoded data and the data content to generate bit correction information; using the encoded data to calculate multiple first branch metrics based on the Viterbi algorithm, the first branch metrics corresponding to a target bit of the data content; adjusting at least one of the first branch metrics based on the data content and the bit correction information to generate multiple second branch metrics; and selecting the first branch metrics or the second branch metrics based on the bit correction information.

Systems, methods, and instrumentalities are disclosed for interleaving coded bits. A wireless transmit/receive unit (WTRU) may generate a plurality of polar encoded bits using polar encoding. The WTRU may divide the plurality of polar encoded bits into sub-blocks of equal size in a sequential manner. The WTRU may apply sub-block wise interleaving to the sub-blocks using an interleaver pattern. The sub-blocks associated with a subset of the sub-blocks may be interleaved, and sub-blocks associated with another subset of the sub-blocks may not be interleaved. The sub-block wise interleaving may include applying interleaving across the sub-blocks without interleaving bits associated with each of the sub-blocks. The WTRU may concatenate bits from each of the interleaved sub-blocks to generate interleaved bits, and store the interleaved bits associated with the interleaved sub-blocks in a circular buffer. The WTRU may select a plurality of bits for transmission from the interleaved bits.

A transmitter is provided. The transmitter includes: a Low Density Parity Check (LDPC) encoder configured to encode input bits to generate parity bits; a parity permutator configured to perform parity permutation by interleaving the parity bits and group-wise interleaving a plurality of bit groups including the interleaved parity bits; and a puncturer configured to select some of the parity bits in the group-wise interleaved bit groups, and puncture the selected parity bits, wherein the parity permutator group-wise interleaves the bit groups such that some of the bit groups are positioned at predetermined positions, respectively, and a remainder of the bit groups are positioned without an order within the group-wise interleaved bit groups so that the puncturer selects parity bits included in the some of the bit groups positioned at the predetermined positions sequentially and selects parity bits included in the remainder of the bit groups without an order.