Disclosed in the present specification is a method for performing channel encoding. The method can comprise the steps of: interleaving information bits; and encoding the interleaved information bits by using a polar code. The information bits can be interleaved according to an interleaving pattern.

A method includes receiving an DSN access request, identifying an DSN address of the DSN access request, identifying one or more DS processing units affiliated with the DSN address. The method further includes selecting a DS processing unit of the one or more DS processing units based on DS processing attributes, determining if the selected DS processing unit is associated with a favorable availability level and, when it is determined that a favorable availability level does not exist, deterministically selecting another of the one or more DS processing units and, when it is determined that a favorable availability level does exist, forwarding the DSN access request to the selected DS processing unit to be processed for storage in one or more DSN storage units.

Systems, methods, and apparatus for enhanced partial processing of satellite user data are disclosed. In one or more embodiments, a disclosed method for processing satellite data comprises encoding with an outer encoder in a transmitting terminal, modulating with a transmit modulator in the transmitting terminal, demodulating with a satellite demodulator in a satellite, encoding with an inner encoder in the satellite, modulating with a satellite modulator in the satellite, demodulating with a receive demodulator in a receiving terminal, decoding with an inner decoder in the receiving terminal, and decoding with an outer decoder in the receiving terminal. In one or more embodiments, the outer encoder and/or the inner encoder is operable to perform forward error correction (FEC) encoding. In at least one embodiment, the outer decoder and/or the inner decoder is operable to perform FEC decoding.

A transmitter is provided. The transmitter includes: a low density parity check (LDPC) encoder configured to encode input bits to generate an LDPC codeword including the input bits and parity bits; a repeater configured to select at least a part of bits constituting the LDPC codeword and add the selected bits after the input bits; and a puncturer configured to puncture at least a part of the parity bits.

Methods and apparatus for selection of memory devices in a distributed storage network. In an example, a computing device receives a data object for storage and selects a set of storage nodes of a plurality of sets of storage nodes for storing the data object. Selection of the set of storage nodes includes determining storage attributes associated with each set of storage nodes of the plurality of sets of storage nodes. Selection of the set of storage nodes additionally includes determining a storage preference associated with the data object, and comparing the storage preference with the storage attributes of the plurality of sets of storage nodes to determine a best match. Following selection of a set of storage nodes, the computing device facilitates storage of the data object in the selected set of storage nodes.

Systems, methods, and apparatus for enhanced partial processing of satellite user data are disclosed. In one or more embodiments, a disclosed method for processing satellite data comprises encoding with an outer encoder in a transmitting terminal, modulating with a transmit modulator in the transmitting terminal, demodulating with a satellite demodulator in a satellite, encoding with an inner encoder in the satellite, modulating with a satellite modulator in the satellite, demodulating with a receive demodulator in a receiving terminal, decoding with an inner decoder in the receiving terminal, and decoding with an outer decoder in the receiving terminal. In one or more embodiments, the outer encoder and/or the inner encoder is operable to perform forward error correction (FEC) encoding. In at least one embodiment, the outer decoder and/or the inner decoder is operable to perform FEC decoding.

A zero padding apparatus and method for variable length signaling information are disclosed. A zero padding apparatus according to an embodiment of the present invention includes a processor configured to generate a LDPC information bit string by deciding a number of groups whose all bits are to be filled with 0 using a difference between a length of the LDPC information bit string and a length of a BCH-encoded bit string, selecting the groups using a shortening pattern order to fill all the bits of the groups with 0, and filling at least a part of remaining groups, which are not filled with 0, with the BCH-encoded bit string; and memory configured to provide the LDPC information bit string to an LDPC encoder.

An apparatus (100) for providing an joint error correction code (140) for a combined data frame (254) comprising first data (112) of a first data channel and second data (122) of a second data channel comprises a first error code generator (110) configured to provide, based on a linear code, information on a first error correction code (114a, 114b) using the first data (112). The apparatus further comprises a second error code generator (120) configured to provide, based on the linear code, information on a second error correction code (124) using the second data (122). The apparatus is configured to provide the joint error correction code (140) using the information on the first error correction code (114a, 114b) and the information on the second error correction code (124).

A rate matching method for a polar code is provided, to improve performance. The method includes: encoding, based on an N*N encoding matrix of a polar code, a sequence including N first bits, to generate a mother code including N second bits, where the N first bits are in a one-to-one correspondence with N rows in the encoding matrix in sequence, and the N second bits are in a one-to-one correspondence with N columns in the encoding matrix in sequence; determining NM to-be-punctured second bits from the N second bits, where at least one first bit in NM first bits participating in encoding of the NM second bits belongs to the first M first bits in the N first bits, and the NM first bits are fixed bits; and puncturing the NM second bits, to obtain a target polar code including M second bits.

A LDPC encoding method is provided, which is highly scalable and may support a variety of code cases and allow a high processing speed. The LDPC encoding includes: receiving an information sequence to be encoded; segmenting the information sequence into blocks of a predetermined length; deriving parity bits for each of the segmented blocks by using a predetermined parity check matrix; and generating a codeword by combining the parity bits into a corresponding segmented block. The operation of deriving parity bits for each of the segmented blocks includes: performing multiplications with at least one element of the parity check matrix by circularly shifting the segmented block a number of times corresponding to the at least one element of the parity check matrix; and performing XOR operations on a plurality of bits of a circularly-shifted segmented block in parallel.